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| ElanTMSC400 and ElanSC410 Single-Chip, Low-Power, PC/AT-Compatible Microcontrollers DISTINCTIVE CHARACTERISTICS ElanTMSC400 and ElanSC410 Microcontrollers s E86TM family of x86 embedded processors s Standard PC/AT system logic (PICs, DMACs, timer, RTC) - DOS, ROM-DOS, Windows, and industrystandard BIOS support - Leverages the benefits of desktop computing environment at embedded price points s Bidirectional parallel port with Enhanced - Offers improved time-to-market, software migration, and field-proven development tools s Highly integrated single-chip CPU with a complete Parallel Port (EPP) mode s 16550-compatible UART s Infrared port for wireless communication set of common peripherals - Accelerates time-to-market with simplified hardware - Low-power 0.35-micron process technology - Single chip delivers smallest system form factor - 33-MHz, 66-MHz, and 100-MHz operating frequencies s Am486(R) CPU core - Standard and high-speed s Keyboard interface - Matrix keyboard support with up to 15 rows and 8 columns - SCP-emulation mode for PC/AT and XT keyboard support - Robust Microsoft(R) Windows(R) compatible CPU - 8-Kbyte write-back cache for enhanced performance - Fully static design with System Management Mode (SMM) for power savings s Comprehensive power management unit ElanSC400 Microcontroller Only The ElanSC400 microcontroller includes the following additional features designed specifically for mobile computing applications. The ElanSC410 microcontroller does not include these features. s Dual PC Card (PCMCIA Version 2.1) controller - Seven modes of operation allow fine-tuning of power requirements for maximum battery life - Provides a superset of APM 1.2 features s Glueless burst-mode supports 8- or 16-bit data bus - End-user (after-market) system expansion - ExCA-compliant, 82365-register set compatible - Leverages off-the-shelf card and socket services - Supports DMA transfers between I/O PC cards and system DRAM s LCD graphics controller ROM/Flash memory/SRAM interface - Reduces system cost by allowing mask ROM and Flash memory at the same time with three ROM/ Flash memory/SRAM chip selects s Glueless DRAM controller - Allows mixed DRAM types on a per-bank basis to reduce system cost s VESA Local (VL) bus and ISA bus interface - Supports monochrome and 4-bit color Super Twisted Nematic (STN) LCDs - Unified Memory Architecture (UMA) eliminates separate video memory - Reduces time-to-market with a wide variety of offthe-shelf companion chips (c) Copyright 1998 Advanced Micro Devices, Inc. All Rights Reserved. Advanced Micro Devices, Inc. ("AMD") reserves the right to discontinue its products, or make changes in its products, at any time without notice. The information in this publication is believed to be accurate at the time of publication, but AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication or the information contained herein, and reserves the right to make changes at any time, without notice. AMD disclaims responsibility for any consequences resulting from the use of the information included in this publication. This publication neither states nor implies any representations or warranties of any kind, including but not limited to, any implied warranty of merchantability or fitness for a particular purpose. AMD's products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of AMD's product could create a situation where personal injury, death, or severe property or environmental damage may occur. AMD assumes no liability whatsoever for claims associated with Publication# 21028 Rev: B Amendment/0 the sale or use (including the use of engineering samples) of AMD products except as provided in AMD's Terms and Conditions Issue Date: December 1998 of Sale for such product. GENERAL DESCRIPTION The ElanTMSC400 and ElanSC410 microcontrollers are the among the latest in a series of E86TM family microcontrollers, which integrate proven x86 CPU cores with a comprehensive set of on-chip peripherals in a 0.35-micron process. The ElanSC400 and ElanSC410 microcontrollers combine a 32-bit, low-voltage Am486 CPU with a complete set of PC/AT-compatible peripherals, along with the power management features required for battery operation. Leveraging the benefits of the x86 desktop computing environment, the ElanSC400 and ElanSC410 microcontrollers integrate all of the common logic and I/O functionality associated with a PC/AT computing system into a single device, eliminating the need for multiple peripheral chips. Fully integrated PC/AT-compatible peripherals include two 8259A-compatible programmable interrupt controllers (PICs), two 8237A-compatible DMA controllers, an 8254-compatible timer, a 16550 UART, an IrDA controller, VL-bus and ISA bus controllers, a real-time clock (RTC), and Enhanced Parallel Port (EPP) mode for the parallel port. With its low-voltage Am486(R) CPU core and ultra-small form factor, the ElanSC400 microcontroller is highly optimized for mobile computing applications. The ElanSC410 microcontroller is targeted specifically for embedded systems. A feature comparison of the two microcontrollers is shown in Table 1 on page 3. The ElanSC400 and ElanSC410 microcontrollers use the industry-standard 486 microprocessor instruction set. All software written for the x86 architecture family is compatible with the ElanSC400 and ElanSC410 microcontrollers. The ElanSC400 and ElanSC410 microcontrollers are based on a fully static design and include an advanced power management unit. Operating voltages are 2.7 V-3.3 V with 5-V-tolerant I/O pads. Orderable in both 33-MHz, 66-MHz, and 100-MHz peak processor speeds, the product is available in the ultra-small 292 ball grid array (BGA) package. ORDERING INFORMATION AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below. ELANSC400 -33 A C TEMPERATURE RANGE C = Commercial For 33 and 66 MHz: TCASE = 0C to +95C For 100 MHz: TCASE = 0C to +85C I = Industrial For 33 and 66 MHz, TCASE = - 40C to +95C PACKAGE TYPE A = 292-pin BGA (Ball Grid Array) SPEED OPTION -33 = 33 MHz -66 = 66 MHz -100 = 100 MHz DEVICE NUMBER/DESCRIPTION ElanSC400 microcontroller ElanSC410 microcontroller Valid Combinations ELANSC400-33 ELANSC400-66 ELANSC400-100 ELANSC410-33 ELANSC410-66 ELANSC410-100 AC AC AC, AI AC, AI Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. 2 ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet Table 1. Product Comparison--ElanSC400 and ElanSC410 Microcontrollers ElanSC410 Am486 CPU 8-Kbyte Write-Back Yes No 16, 32 bit 8, 16 bit No 32 bit No Yes Yes Yes Yes Yes 8, 16, 32 bit 3 x 64 Mbyte 3 Yes Yes 4 16, 32 bit 64 Mbyte Yes ROM-mappable Yes Yes Yes 2 8, 16 bit 7 2 2 8 Yes 16550-compatible Yes Yes Yes 32 Yes No ElanSC400 Am486 CPU 8-Kbyte Write-Back Yes No 16, 32 bit 8, 16 bit No 32 bit No Yes Yes Yes Yes Yes 8, 16, 32 bit 3 x 64 Mbyte 3 Yes Yes 4 16, 32 bit 64 Mbyte Yes ROM-mappable Yes Yes Yes 2 8, 16 bit 7 2 2 8 Yes 16550-compatible Yes Yes Yes 32 Yes Yes 2 Yes Yes Yes Yes Yes Yes 292 BGA 2.7-3.3 V 3.3 V 5V 33, 66, 100 MHz Feature Core CPU L1 Cache System management mode (SMM) Floating-point unit Data Bus ISA Interface ISA bus mastering VESA Local Bus VL bus mastering Power Management Mode timers Activity detection SMI/NMI generation Battery monitoring On-Chip ROM Interface Width Size (total ROM space) ROM chip selects Burst-mode support Support for SRAM as ROM address space On-Chip DRAM Controller Banks Width Size (total of all banks) EDO support Support for SRAM as main memory Integrated PC/AT-Compatible Peripherals Programmable timer (8254-compatible) Real-time clock (146818A-compatible) Port B and Port 92h I/O registers Cascaded DMA Controllers (8237A) Width Total number of channels External channels Cascaded Interrupt Controllers (8259) External IRQ signals Bidirectional Parallel Port with EPP Mode Serial Port (UART) Keyboard Interface Support for external 8042 SCP XT interface Matrix scanned with SCP emulation General-Purpose Input/Output Signals Infrared (IrDA) Port PC Card Controller Sockets PCMCIA 2.1-compliant 82365-compatible LCD Graphics Controller Programmable clock frequency Unified memory architecture (UMA) JTAG Support Pin Count and Package VCC: CPU core On-chip peripheral logic I/O tolerance (designated pins) Processor Clock Rate No Yes 292 BGA 2.7-3.3 V 3.3 V 5V 33, 66, 100 MHz ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet 3 BLOCK DIAGRAM--ElanSC400 MICROCONTROLLER ElanSC400 Microcontroller Addr Data Am486(R) CPU Memory Management Unit System Address Bus Address Decoder Addr Dual DMA Controllers 8237 Data Steering Data Bus Power GPIOs Management Unit Clock I/O Clock Generation Real-Time Clock Boundary Scan AT Port Logic Timer 8254 Dual Interrupt Controllers 8259 Socket A Ctrl GPIOs or Parallel Port or PC Card Socket B PC Card Controller GPIOs EPP Parallel Port UART 16550 Infrared Port GPIOs GPIOs Internal Bus LCD Graphics Controller Graphics or Local Bus Controller Local Bus Controller 32-kHz Crystal System Arbiter GPIOs DRAM Control Memory Controller ROM Control DRAM Control or Keyboard Rows GPIOs or Keyboard Rows Columns or XT Keyboard ISA Control or Keyboard Rows ISA Control ISA Control or GPIOs Keyboard Interface: Matrix/XT/SCP Serial Port ISA Bus Controller Infrared 4 ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet BLOCK DIAGRAM--ElanSC410 MICROCONTROLLER ElanSC410 Microcontroller Addr Data Am486(R) CPU Memory Management Unit System Address Bus Address Decoder Addr Dual DMA Controllers 8237 Data Steering Data Bus Power GPIOs Management Unit Clock I/O Clock Generation Real-Time Clock Boundary Scan AT Port Logic Timer 8254 Dual Interrupt Controllers 8259 GPIOs or Parallel Port EPP Parallel Port Serial Port UART 16550 Infrared Port GPIOs Memory Controller Internal Bus 32-kHz Crystal Local Bus Controller Local Bus Controller System Arbiter GPIOs DRAM Control ROM Control DRAM Control or Keyboard Rows GPIOs Keyboard Interface: Matrix/XT/SCP GPIOs or Keyboard Rows Columns or XT Keyboard ISA Control or Keyboard Rows ISA Control ISA Control or GPIOs ISA Bus Controller GPIOs Infrared ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet 5 LOGIC SYMBOL--ElanSC400 MICROCONTROLLER LCDD7 [VL_BE3] LCDD6 [VL_LDEV] LCDD5 [VL_D/C] LCDD4 [VL_LRDY] LCDD3 [VL_M/IO] LCDD2 [VL_W/R] MWE CASL/H1-CASL/H0 RAS1-RAS0 MA11-MA5 MA4 MA3 {CFG3} MA2 {CFG2} MA1 {CFG1} MA0 {CFG0} D15-D0 SD15-SD0 [D31-D16] SA25-SA0 ROMCS1-ROMCS0 ROMRD ROMWR IOR IOW MEMR MEMW RSTDRV MCEL_A [[BNDSCN_TCK]] MCEH_A [[BNDSCN_TMS]] RST_A [[BNDSCN_TDI]] REG_A [[BNDSCN_TDO]] LCD Graphics Controller or VESA Local Bus LCDD1 [VL_ADS] LCDD0 [VL_RST] M [VL_BE2] LC [VL_BE1] SCK [VL_BE0] FRM [VL_LCLK] LVEE [VL_BRDY] LVDD [VL_BLAST] DTR, RTS, SOUT DRAM Interface and Feature Configuration Pins DRAM, VL, ROM, ISA and PC Card Data VL, ROM, ISA, and PC Card Address ROM/Flash Memory Control PC Card Command ISA Bus Command and Reset 8-Pin Serial Port Infrared Interface Power Management Interface GPIOs GPIO/External Buffer Control CTS, DCD, DSR RIN, SIN SIROUT SIRIN ACIN BL2-BL1 BL0 [CLK_IO] GPIO_CS0 GPIO_CS1 GPIO_CS2 [[DBUFRDL]] GPIO_CS3 [[DBUFRDH]] GPIO_CS4 [[DBUFOE]] GPIO_CS5 [IOCS16] GPIO/ISA Interface GPIO_CS6 [IOCHRDY] GPIO_CS7 [PIRQ1] GPIO_CS8 [PIRQ0] GPIO_CS9 [TC] GPIO_CS10 [AEN] GPIO_CS11 [PDACK0] GPIO_CS12 [PDRQ0] GPIO_CS13 [PCMA_VCC] GPIO_CS14 [PCMA_VPP1] GPIO15 [PCMA_VPP2] ElanSC400 Microcontroller 292 BGA CD_A RDY_A BVD1_A, BVD2_A WP_A WAIT_AB OE WE ICDIR GPIO31 [STRB] [MCEL_B] GPIO30 [AFDT] [MCEH_B] GPIO29 [SLCTIN] [RST_B] GPIO28 [INIT] [REG_B] GPIO27 [ERROR] [CD_B] GPIO26 [PE] [RDY_B] GPIO25 [ACK] [BVD1_B] GPIO24 [BUSY] [BVD2_B] GPIO23 [SLCT] [WP_B] GPIO22 [PPOEN] GPIO21 [PPDWE] 32KXTAL1, 32KXTAL2 LF_INT, LF_LS LF_VID, LF_HS RESET VCC_RTC BBATSEN Dedicated Single Slot PC Card and Boundary Scan Interface GPIO/PC Card Power Control GPIO16 [PCMB_VCC] GPIO17 [PCMB_VPP1] GPIO18 [PCMB_VPP2] GPIO19 [LBL2] GPIO20 [CD_A2] KBD_COL7 KBD_COL6-2 / PIRQ7-3 KBD COL1-0 [XT_CLK/DATA] SUS_RES / KBD_ROW14 KBD_ROW13 [[R32BFOE]] KBD_ROW12 [MCS16] Parallel Port or Second PC Card or GPIOs Scan Keyboard Columns/IRQs/XT Keyboard Interface Scan Keyboard Rows/ISA Interface KBD_ROW11 [SBHE] KBD_ROW10 [BALE] KBD_ROW9 [PIRQ2] KBD_ROW8 [PDRQ1] KBD_ROW7 [PDACK1] KBD_ROW6 [MA12] KBD_ROW5 [RAS3] 32-kHz Crystal Loop Filters Reset RTC Scan Keyboard Rows/DRAM Interface KBD_ROW4 [RAS2] KBD_ROW3 [CASH3] KBD_ROW2 [CASH2] KBD_ROW1 [CASL3] BNDSCN_EN KBD_ROW0 [CASL2] SPKR Speaker Boundary Scan Enable Notes: / =Two functions available on the pin at the same time. { } = Function during hardware reset. [ ] = Alternative function selected by firmware configuration. [[ ]] = Alternate function selected by a hardware configuration pin state at power-on reset. This does not apply to [[BNDSCN_TCK]], [[BNDSCN_TMS]], [[BNDSCN_TDI]], and [[BNDSCN_TDO]]. These alternate functions are enabled by the BNDSCN_EN signal. 6 ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet LOGIC SYMBOL--ELANSC410 MICROCONTROLLER VL_BE3 VL_LDEV VL_D/C VL_LRDY VL_M/IO VL_W/R MWE CASL/H1-CASL/H0 RAS1-RAS0 MA11-MA5 MA4 MA3 {CFG3} MA2 MA1 {CFG1} MA0 {CFG0} D15-D0 SD15-SD0 [D31-D16] SA25-SA0 VESA Local Bus VL_ADS VL_RST VL_BE2 VL_BE1 VL_BE0 VL_LCLK VL_BRDY VL_BLAST DTR, RTS, SOUT DRAM Interface and Feature Configuration Pins DRAM, VL, ROM, and ISA Data VL, ROM, and ISA Address ROM/Flash Memory Control 8-Pin Serial Port Infrared Interface Power Management Interface GPIOs GPIO/External Buffer Control CTS, DCD, DSR RIN, SIN SIROUT SIRIN ACIN BL2-BL1 BL0 [CLK_IO] GPIO_CS0 GPIO_CS1 GPIO_CS2 [[DBUFRDL]] GPIO_CS3 [[DBUFRDH]] GPIO_CS4 [[DBUFOE]] GPIO_CS5 [IOCS16] ROMCS1-ROMCS0 ROMRD ROMWR IOR IOW MEMR MEMW RSTDRV ISA Bus Command and Reset [[BNDSCN_TCK]] [[BNDSCN_TMS]] GPIO/ISA Interface GPIO_CS6 [IOCHRDY] GPIO_CS7 [PIRQ1] GPIO_CS8 [PIRQ0] GPIO_CS9 [TC] GPIO_CS10 [AEN] GPIO_CS11 [PDACK0] GPIO_CS12 [PDRQ0] GPIO_CS13 GPIO_CS14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 [LBL2] GPIO20 ElanSC410 Microcontroller 292 BGA [[BNDSCN_TDI]] [[BNDSCN_TDO]] Boundary Scan Interface GPIO31 [STRB] GPIO30 [AFDT] GPIO29 [SLCTIN] GPIO28 [INIT] GPIO27 [ERROR] GPIO26 [PE] GPIO25 [ACK] GPIO24 [BUSY] GPIO23 [SLCT] GPIO22 [PPOEN] Parallel Port or GPIOs GPIO/ Power Control Scan Keyboard Columns/IRQs/XT Keyboard Interface KBD_COL7 KBD_COL6-2 / PIRQ7-3 KBD COL1-0 [XT_CLK/DATA] SUS_RES / KBD_ROW14 KBD_ROW13 [[R32BFOE]] KBD_ROW12 [MCS16] GPIO21 [PPDWE] 32KXTAL1, 32KXTAL2 LF_INT, LF_LS LF_HS 32-kHz Crystal Loop Filters Scan Keyboard Rows/ISA Interface KBD_ROW11 [SBHE] KBD_ROW10 [BALE] KBD_ROW9 [PIRQ2] KBD_ROW8 [PDRQ1] KBD_ROW7 [PDACK1] KBD_ROW6 [MA12] KBD_ROW5 [RAS3] RESET Reset VCC_RTC BBATSEN RTC Scan Keyboard Rows/DRAM Interface KBD_ROW4 [RAS2] KBD_ROW3 [CASH3] KBD_ROW2 [CASH2] KBD_ROW1 [CASL3] BNDSCN_EN SPKR Speaker Boundary Scan Enable KBD_ROW0 [CASL2] Notes: / =Two functions available on the pin at the same time. { } = Function during hardware reset. [ ] = Alternative function selected by firmware configuration. [[ ]] = Alternate function selected by a hardware configuration pin state at power-on reset. This does not apply to [[BNDSCN_TCK]], [[BNDSCN_TMS]], [[BNDSCN_TDI]], and [[BNDSCN_TDO]]. These functions are enabled by the BNDSCN_EN signal. ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet 7 TABLE OF CONTENTS Distinctive Characteristics ............................................................................................................ 1 ElanTMSC400 and ElanSC410 Microcontrollers ...................................................................... 1 ElanSC400 Microcontroller Only ............................................................................................. 1 General Description ..................................................................................................................... 2 Block Diagram--ElanSC400 Microcontroller .............................................................................. 4 Block Diagram--ElanSC410 Microcontroller .............................................................................. 5 Logic Symbol--ElanSC400 Microcontroller ................................................................................. 6 Logic Symbol--ElanSC410 Microcontroller ................................................................................. 7 Related AMD Products .............................................................................................................. 12 E86TM Family Devices ........................................................................................................... 12 Related Documents ............................................................................................................... 12 ElanTMSC400 Microcontroller Evaluation Board ................................................................... 13 Third-Party Development Support Products ...................................................................................13 Customer Service .................................................................................................................. 13 Architectural Overview ............................................................................................................... 13 Low-Voltage Am486 CPU Core ............................................................................................ 14 Power Management .............................................................................................................. 14 Clock Generation .................................................................................................................. 14 ROM/Flash Memory Interface ............................................................................................... 15 DRAM Controller ................................................................................................................... 15 Integrated Standard PC/AT Peripherals ................................................................................ 15 PC/AT Support Features ....................................................................................................... 16 Bidirectional Enhanced Parallel Port (EPP) .......................................................................... 16 Serial Port .............................................................................................................................. 17 Keyboard Interfaces .............................................................................................................. 17 Programmable General-Purpose Inputs and Outputs ........................................................... 17 Infrared Port for Wireless Communication ............................................................................ 17 Dual PC Card Controller (ElanSC400 Microcontroller Only) ................................................. 17 Graphics Controller for CGA-Compatible Text and Graphics (ElanSC400 Microcontroller Only) .. 17 JTAG Test Features .............................................................................................................. 18 System Interfaces ................................................................................................................. 18 System Considerations .............................................................................................................. 20 Connection Diagram--ElanSC400 and ElanSC410 Microcontrollers ........................................ 24 Pin Designations ........................................................................................................................ 25 Pin Naming ............................................................................................................................ 25 Pin Changes for the ElanSC410 Microcontroller ....................................................................... 25 Pin Designations (Pin Number)--ElanSC400 Microcontroller ................................................... 26 Pin Designations (Pin Name)--ElanSC400 Microcontroller ...................................................... 29 Pin Designations (Pin Number)--ElanSC410 Microcontroller ................................................... 33 Pin Designations (Pin Name)--ElanSC410 Microcontroller ...................................................... 36 Pin State Tables ........................................................................................................................ 40 Pin Characteristics ................................................................................................................ 40 Using the Pin State Tables .................................................................................................... 41 Signal Descriptions .................................................................................................................... 62 Multiplexed Pin Function Options .......................................................................................... 70 Using the Configuration Pins to Select Pin Functions............................................................ 74 Clocking ..................................................................................................................................... 76 Clock Generation .................................................................................................................. 76 Integrated Peripheral Clock Sources .................................................................................... 77 32-kHz Crystal Oscillator ....................................................................................................... 79 Loop Filters ........................................................................................................................... 79 Intermediate and Low-Speed PLLs ....................................................................................... 79 Graphics Dot Clock PLL (ElanSC400 Microcontroller Only) ................................................. 80 8 ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet High-Speed PLL .................................................................................................................... 81 Band Gap Block .................................................................................................................... 81 RTC Voltage Monitor ............................................................................................................. 81 Clock Specifications .............................................................................................................. 83 Absolute Maximum Ratings ....................................................................................................... 86 Operating Ranges ...................................................................................................................... 86 DC Characteristics Over Commercial and Industrial Operating Ranges .................................... 86 Capacitance ............................................................................................................................... 87 Typical Power Numbers ............................................................................................................. 88 Power Requirements Under Different Power Management Modes ...................................... 88 Derating Curves ......................................................................................................................... 89 AC Switching Characteristics and Waveforms .......................................................................... 91 Key to Switching Waveforms ................................................................................................ 91 AC Switching Test Waveforms .................................................................................................. 91 AC Switching Characteristics over Commercial and Industrial Operating Ranges ............... 92 Thermal Characteristics ........................................................................................................... 130 Physical Dimensions--BGA 292--Plastic Ball Grid Array ...................................................... 131 LIST OF FIGURES Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Typical Mobile Terminal Design ............................................................................. 21 System Diagram with Trade-offs--ElanSC400 Microcontroller ............................. 22 System Design with Trade-offs--ElanSC410 Microcontroller ............................... 23 Clock Generation Block Diagram ........................................................................... 76 Clock Source Block Diagram ................................................................................. 78 32-kHz Crystal Circuit ............................................................................................ 79 32-kHz Oscillator Circuit ........................................................................................ 79 Intermediate and Low-Speed PLLs Block Diagram ............................................... 80 Graphics Dot Clock PLL Block Diagram ................................................................ 81 High-Speed PLL Block Diagram ............................................................................ 82 RTC Voltage Monitor Circuit .................................................................................. 82 Timing Diagram for RTC-On Power-Down Sequence ........................................... 83 PLL Enabling Timing Sequence ............................................................................ 85 3.3-V I/O Drive Type A Rise Time ......................................................................... 89 3.3-V I/O Drive Type A Fall Time ........................................................................... 89 3.3-V I/O Drive Type B Rise Time ......................................................................... 89 3.3-V I/O Drive Type B Fall Time ........................................................................... 89 3.3-V I/O Drive Type C Rise Time ......................................................................... 90 3.3-V I/O Drive Type C Fall Time ........................................................................... 90 3.3-V I/O Drive Type D Rise Time ......................................................................... 90 3.3-V I/O Drive Type D Fall Time ........................................................................... 90 3.3-V I/O Drive Type E Rise Time ......................................................................... 90 3.3-V I/O Drive Type E Fall Time ........................................................................... 90 Power-Up Timing Sequence .................................................................................. 92 Fast Mode 8-/16-/32-Bit ROM/Flash Memory Read Cycle .................................... 94 Fast Mode CPU Read of Three Consecutive Bytes from 8-Bit ROM/Flash Memory .. 95 Fast Mode 8-/16-/32-Bit Flash Memory Write Cycles ............................................ 95 Fast Mode 16-Bit Burst ROM Read Cycles ........................................................... 96 Fast Mode CPU Burst Read from 32-Bit Burst Mode ROM/Flash Memory ........... 96 Normal Mode 8-/16-Bit ROM/Flash Memory Read Cycles .................................... 97 Normal Mode 8-/16-Bit Flash Memory Write Cycles .............................................. 97 DRAM Page Hit Read, Interleaved ........................................................................ 99 DRAM Page Hit Write, Interleaved ........................................................................ 99 DRAM Page Miss Read, Interleaved ................................................................... 100 ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet 9 Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. DRAM Page Hit Read, Non-Interleaved .............................................................. 100 DRAM Page Hit Write, Non-Interleaved .............................................................. 101 DRAM Page Miss Read, Non-Interleaved ........................................................... 101 EDO DRAM Page Hit Read, Non-Interleaved ..................................................... 102 EDO DRAM Page Miss Read, Non-Interleaved .................................................. 102 DRAM CAS-Before-RAS Refresh ........................................................................ 103 DRAM Self-Refresh ............................................................................................. 103 DRAM Slow Refresh ............................................................................................ 104 8-Bit ISA Bus Cycles ............................................................................................ 107 16-Bit ISA Bus Cycles .......................................................................................... 108 ISA DMA Read Cycle .......................................................................................... 109 ISA DMA Write Cycle ........................................................................................... 110 VESA Local Bus Cycles ....................................................................................... 112 EPP Parallel Port Write Cycle .............................................................................. 114 EPP Parallel Port Read Cycle ............................................................................. 115 I/O Decode (R/W), Address Decode Only ........................................................... 116 I/O Decode (R/W), Command Qualified .............................................................. 116 I/O Decode (R/W), GPIO_CSx as 8042CS Timing .............................................. 117 Memory CS Decode (R/W), Address Decode Only ............................................. 117 Memory CS Decode (R/W), Command Qualified ................................................ 118 PC Card Attribute Memory Read Cycle (ElanSC400 Microcontroller Only) ........ 120 PC Card Attribute Memory Write Cycle (ElanSC400 Microcontroller Only) ......... 121 PC Card Common Memory Read Cycle (ElanSC400 Microcontroller Only) ....... 122 PC Card Common Memory Write Cycle (ElanSC400 Microcontroller Only) ....... 123 PC Card I/O Read Cycle ...................................................................................... 124 PC Card I/O Write Cycle ...................................................................................... 125 PC Card DMA Read Cycle (Memory Read to I/O Write) ..................................... 126 PC Card DMA Write Cycle (I/O Read to Memory Write) ..................................... 127 Graphics Panel Interface Timing (ElanSC400 Microcontroller Only) ................... 128 Graphics Panel Power Sequencing (ElanSC400 Microcontroller Only) .............. 129 LIST OF TABLES Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. 10 Product Comparison--ElanSC400 and ElanSC410 Microcontrollers ...................... 3 Drive Output Description ........................................................................................ 40 Pin Type Abbreviations .......................................................................................... 40 Power Pin Type Abbreviations ............................................................................... 41 Power-Down Groups ............................................................................................. 41 Pin State Table--System Interface ........................................................................ 42 Pin State Table--Memory Interface ....................................................................... 44 Pin State Table--GPIOs/Parallel Port/PC Card Socket B ..................................... 47 Pin State Table--GPIOs/ISA Bus .......................................................................... 49 Pin State Table--GPIOs/System Data (SD) Buffer Control ................................... 51 Pin State Table--GPIOs ........................................................................................ 52 Pin State Table--Serial Port .................................................................................. 52 Pin State Table--Infrared Interface ....................................................................... 52 Pin State Table--Keyboard Interface .................................................................... 53 Pin State Table--PC Card Socket A ..................................................................... 55 Pin State Table--Graphics Controller/VESA Local Bus Control ............................ 56 Pin State Table--Miscellaneous ............................................................................ 58 Pin State Table--Power and Ground .................................................................... 59 Signal Description Table ........................................................................................ 62 Multiplexed Pin Configuration Options ................................................................... 70 Pinstrap Bus Buffer Options .................................................................................. 74 ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. CFG0 and CFG1 Configuration ............................................................................. 74 CFG2 Configuration (ElanSC400 microcontroller only) ......................................... 74 CFG3 Configuration ............................................................................................... 75 BNDSCN_EN Configuration .................................................................................. 75 Integrated Peripheral Clock Sources ..................................................................... 77 Frequency Selection Control for Graphics Dot Clock PLL ..................................... 80 Loop-Filter Component Specification for PLLs ...................................................... 84 Analog VCC (VCCA) Specification ......................................................................... 84 32.768-kHz Crystal Characteristics ....................................................................... 84 Start-Up Time Specifications PLLs ........................................................................ 84 PLL Jitter Specification .......................................................................................... 85 Operating Voltage (Commercial and Industrial) ..................................................... 87 Power Estimates .................................................................................................... 88 Power-On Reset Cycle .......................................................................................... 92 ROM/Flash Memory Cycles ................................................................................... 93 DRAM Cycles ........................................................................................................ 98 ISA Cycles ........................................................................................................... 105 VESA Local Bus Cycles ....................................................................................... 111 Parallel Port Cycles ............................................................................................. 113 General-Purpose Input/Output Cycles ................................................................. 115 PC Card Cycles--ElanSC400 Microcontroller Only ............................................ 119 PC Card Attribute Memory Read Function (ElanSC400 Microcontroller Only) .... 120 PC Card Attribute Memory Write Function (ElanSC400 Microcontroller Only) .... 121 PC Card Common Memory Read Function (ElanSC400 Microcontroller Only) .. 122 PC Card Common Memory Write Function (ElanSC400 Microcontroller Only) ... 123 PC Card I/O Read Function (ElanSC400 Microcontroller Only) .......................... 124 PC Card I/O Write Function (ElanSC400 Microcontroller Only) .......................... 125 PC Card DMA Read Function (ElanSC400 Microcontroller Only) ....................... 126 PC Card DMA Write Function (ElanSC400 Microcontroller Only) ....................... 127 LCD Graphics Controller Cycles--ElanSC400 Microcontroller Only ................... 128 Thermal Resistance J-T and JA (C/W) for the 292-BGA Package) ................. 130 Maximum TA at Various Airflows in C ................................................................ 130 ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet 11 RELATED AMD PRODUCTS E86TM Family Devices Device 80C186 80C188 80L186 80L188 Description 16-bit microcontroller 16-bit microcontroller with 8-bit external data bus Low-voltage, 16-bit microcontroller Low-voltage, 16-bit microcontroller with 8-bit external data bus Am186TMEM High-performance, 80C186-compatible, 16-bit embedded microcontroller Am188TMEM High-performance, 80C188-compatible, 16-bit embedded microcontroller with 8-bit external data bus Am186EMLV High-performance, 80C186-compatible, low-voltage, 16-bit embedded microcontroller Am188EMLV High-performance, 80C188-compatible, low-voltage, 16-bit embedded microcontroller with 8-bit external data bus Am186ES Am188ES High-performance, 80C186-compatible, 16-bit embedded microcontroller High-performance, 80C188-compatible, 16-bit embedded microcontroller with 8-bit external data bus Am186ESLV High-performance, 80C186-compatible, low-voltage, 16-bit embedded microcontroller Am188ESLV High-performance, 80C188-compatible, low-voltage, 16-bit embedded microcontroller with 8-bit external data bus Am186ED High-performance, 80C186- and 80C188-compatible, 16-bit embedded microcontroller with 8- or 16-bit external data bus Am186EDLV High-performance, 80C186- and 80C188-compatible, low-voltage, 16-bit embedded microcontroller with 8- or 16-bit external data bus Am186ER Am188ER Am186CC Am186CH Am186CU ElanSC310 ElanSC400 ElanSC410 Am386(R)DX Am386(R)SX Am486(R)DX High-performance, 80C186-compatible, low-voltage, 16-bit embedded microcontroller with 32 Kbyte of internal RAM High-performance, 80C188-compatible, low-voltage, 16-bit embedded microcontroller with 8-bit external data bus and 32 Kbyte of internal RAM High-performance, 80C186-compatible 16-bit embedded communications controller High-performance, 80C186-compatible 16-bit embedded HDLC microcontroller High-performance, 80C186-compatible 16-bit embedded USB microcontroller High-performance, single-chip, 32-bit embedded PC/AT microcontroller Single-chip, low-power, PC/AT-compatible microcontroller Single-chip, PC/AT-compatible microcontroller High-performance, 32-bit embedded microprocessor with 32-bit external data bus High-performance, 32-bit embedded microprocessor with 16-bit external data bus High-performance, 32-bit embedded microprocessor with 32-bit external data bus ElanTMSC300 High-performance, highly integrated, low-voltage, 32-bit embedded microcontroller Related Documents The following documents provide additional information regarding the ElanSC400 and ElanSC410 microcontrollers. s ElanSC400 and ElanSC410 User's Manual, order #21030 s ElanSC400 Register Set Reference Manual, order #21032 s ElanSC400 Register Set Reference Amendment, order #21032A/1 s ElanSC400 Evaluation Board User's Manual, order #21906 s ElanSC400 Microcontroller and Windows CE forCE Demonstration System User's Manual, order #21892 s ROMCS0 Redirection to PC Card Socket A on the ElanSC400 Microcontroller Application Note, order #21643 Manual 12 ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet ElanTMSC400 Microcontroller Evaluation Board The ElanTMSC400 microcontroller evaluation board is a stand-alone evaluation platform for the ElanSC400 and ElanSC410 microcontrollers. As a test and development platform for designs based on the ElanSC400 and ElanSC410 microcontrollers, this AMD product is used by system designers to experiment with design trade-offs, make power measurements, and develop software. Contact your local AMD sales office for more information on evaluation board availability and pricing. World Wide Web Home Page To access the AMD home page, go to: www.amd.com. Then follow the Embedded Processors link for information about E86 and Comm86 products. Questions, requests, and input concerning AMD's WWW pages can be sent via e-mail to webmaster@amd.com. Documentation and Literature Free information such as data books, user's manuals, data sheets, application notes, the E86TM Family Products and Development Tools CD, order #21058, and other literature is available with a simple phone call. Internationally, contact your local AMD sales office for product literature. Additional contact information is listed on the back of this data sheet. Literature Ordering (800) 222-9323 (512) 602-5651 (512) 602-7639 Toll-free for U.S. and Canada Direct dial worldwide Fax Third-Party Development Support Products The FusionE86 S M Program of Partnerships for Application Solutions provides the customer with an array of products designed to meet critical time-tomarket needs. Products and solutions available from the AMD FusionE86 partners include protocol stacks, emulators, hardware and software debuggers, boardlevel products, and software development tools, among others. In addition, mature development tools and applications for the x86 platform are widely available in the general marketplace. ARCHITECTURAL OVERVIEW The architectural goals of the ElanSC400 and ElanSC410 microcontrollers included a focus on CPU performance, CPU-to-memory performance, and internal graphics controller (ElanSC400 microcontroller only) performance. The resulting architecture includes several distinguishing features of interest to the system designer: s The main system DRAM is shared between the CPU and graphics controller, so that the graphics controller can be serviced quickly to maintain video display performance at higher panel resolutions. The internal unified memory architecture (UMA) implemented on the ElanSC400 and ElanSC410 microcontrollers means lower cost and less complication for the system designer, with only one DRAM interface, fewer pins, and a much smaller board for many designs. s CPU-to-memory performance is critical for both DRAM and ROM accesses. The CPU on the ElanSC400 microcontroller has a concurrent path to the ROM/Flash memory interface and can execute code out of ROM/Flash memory at the same time as the graphics controller is accessing DRAM for a screen refresh. Many system designs can take advantage of this concurrency without sacrificing performance. Customer Service The AMD customer service network includes U.S. offices, international offices, and a customer training center. Expert technical assistance is available from the AMD worldwide staff of field application engineers and factory support staff to answer E86TM and Comm86TM family hardware and software development questions. Hotline and World Wide Web Support For answers to technical questions, AMD provides e-mail support as well as a toll-free number for direct access to our corporate applications hotline. The AMD World Wide Web home page provides the latest product information, including technical information and data on upcoming product releases. In addition, EPD CodeKit software on the Web site provides tested source code example applications. Corporate Applications Hotline (800) 222-9323 44-(0) 1276-803-299 Toll-free for U.S. and Canada U.K. and Europe hotline Additional contact information is listed on the back of this datasheet. For technical support questions on all E86 and Comm86 products, send e-mail to epd.support@amd.com. ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet 13 s The ROM/Flash memory interface provides the flexibility to optimize the performance of ROM cycles, including the support of burst-mode ROMs. This is ben efi ci al bec aus e p ro duc ts bas ed on th e ElanSC400 and ElanSC410 microcontrollers may be implemented such that the operating system or application programs are executed from ROM. s Because the microcontrollers support a large number of external buses and interfaces, the address and data buses are shared between the various interfaces to reduce pin count on the chip. These features result in a versatile architecture that can use various combinations of data bus sizes to achieve cost and performance goals. The architecture provides maximum performance and flexibility for highend vertical applications, but contains functionality for a wider horizontal market that may demand less performance. s A typical lower performance/lower cost system might implement 16-bit DRAM banks, an 8-bit ISA bus, an 8/16-bit PC Card bus, and use the internal graphic controller. s A higher performance, full-featured system might include 32-bit DRAM, VL-bus to an external graphics controller, and a 16-bit ISA/PC Card bus. The following basic data bus configuration rules apply. (A complete list of feature trade-offs to be considered in system design can be found in "System Considerations" on page 20.) s When the internal graphics controller on the ElanSC400 microcontroller is enabled, DRAM is always 16 bits wide, and no 32-bit targets are supported. This is because the graphics controller needs a guaranteed short latency for adequate video performance. If either 32-bit DRAMs, 32-bit ROMs, or the VL-bus is enabled, the internal graphics controller is unavailable. Note that, as a derivative of the original ElanSC400 microcontroller, the ElanSC410 microcontroller shares the primary architectural characteristics of the ElanSC400 microcontroller described above, minus the graphics controller and PCMCIA interfaces. The following sections provide an overview of the features of the ElanSC400 and ElanSC410 microcontrollers, including on-chip peripherals and system interfaces. tem performance by significantly reducing traffic on the DRAM bus. s System management mode (SMM) facilitates designs requiring power management by providing a mechanism to control power to unneeded peripherals transparently to application software. To reduce power consumption, the floating-point unit has been removed from the Am486 CPU core. Floating-point instructions are not supported on the ElanSC400 and ElanSC410 microcontrollers, although normal software emulation can be easily implemented. The ElanSC400 and ElanSC410 microcontrollers use the industry-standard 486 instruction set. Software written for the 486 microprocessor and previous members of the x86 architecture family can run on the ElanSC400 and ElanSC410 microcontrollers. Power Management Power management on the ElanSC400 and ElanSC410 microcontrollers includes a dedicated power management unit and additional power management features built into each integrated peripheral. The ElanSC400 and ElanSC410 microcontrollers can use the following techniques to conserve power: s Slow down clocks when the system is not in active use s Shut off clocks to parts of the chip that are idle s Switch off power to parts of the system that are idle s Automatically reduce power use when batteries are low The power management unit (PMU) controls stopping and changing clocks, SMI generation, timers, activities, and battery-level monitoring. It provides: s Hyper-Speed, High-Speed, Low-Speed, Temporary Low-Speed, Standby, Suspend, and Critical Suspend modes s Dynamically adjusted clock speeds for power reduction s Programmable activity and wake-up monitoring s General-purpose I/O signals to control external devices and external power management s Battery low and AC power monitoring s SMI/NMI synchronization and generation Clock Generation The ElanSC400 and ElanSC410 microcontrollers require only one 32.768-kHz crystal to generate all the other clock frequencies required by the system. The output of the on-chip crystal oscillator circuit is used to generate the various frequencies by utilizing four Phase-Locked Loop (PLL) circuits (three for the ElanSC410 microcontroller). An additional PLL in the CPU is used for Hyper-Speed mode. Low-Voltage Am486 CPU Core The ElanSC400 and ElanSC410 microcontrollers are based on the low-voltage Am486 CPU core. The core includes the following features: s 2.7-3.3-V operation reduces power consumption s Industry-standard 8-Kbyte unified code and data write-back cache improves both CPU and total sys- 14 ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet ROM/Flash Memory Interface The integrated ROM/Flash memory interface supports the following features: s 8-, 16-, and 32-bit ROM/Flash memory interfaces s Three ROM/Flash memory chip selects s Burst-mode ROMs s ROM accesses at both ISA and CPU speeds (normal and fast-speed modes) s Dedicated ROM Read and ROM Write signals for better performance Each ROM space can accommodate up to 64 Mbyte of ROM. The three ROM spaces can be individually writeprotected. This is useful for protecting code residing in Flash memory devices. Two of the three ROM/Flash memory chip selects can be remapped to a PC Card socket via pinstrap or software control. This feature supports reprogramming of soldered-down Flash memory boot devices and also simplifies testing of BIOS/XIP OS code. Three ROM access modes are supported: Normal mode, Fast mode, and Burst mode. A different set of timings is used in each mode. In Normal ROM access mode, the bus cycles follow ISA-like timings. In Fast ROM access mode, the bus cycle timing occurs at the CPU clock rate with controls for wait-state insertion. Burst ROM access timing is used when the ROM/Flash memory interface is fulfilling an internal CPU burst request to support a cache line refill. Wait states are supported for all ROM and Flash memory accesses, including Burst mode. Burst-mode (page-mode) ROM reads are supported for either a 16- or 32-bit ROM interface running in Fast mode. s Fast page and Extended Data Out (EDO) DRAMs s Two-way interleaved operation among identically populated banks using fast-page mode devices s Mixed depth and width of DRAM banks in non-interleaved mode s Symmetrical and asymmetrical DRAM support Integrated Standard PC/AT Peripherals The ElanSC400 and ElanSC410 microcontrollers include all the standard peripheral controllers that make up a PC/AT system. Dual DMA Controllers Dual, cascaded, 8237A-compatible DMA controllers provide seven user-definable DMA channels. Of the seven internal channels, four are 8-bit channels and three are 16-bit channels. Channel 4 is used for the cascade function. Any two of the seven channels can be mapped simultaneously to external DMA request/acknowledge lines. The DMA controller on the ElanSC400 and ElanSC410 microcontrollers is software compatible with the PC/AT cascaded 8237 controller pair. Its features include: s Single, block, and demand transfer modes s Enable/disable channel controller s Address increment or decrement s Software priority s 64-Mbyte system address space for increased performance s Dynamic clock-enable design for reducing clocked elements during DMA inactivity s Programmable clock frequency for performance Dual Interrupt Controllers Dual, cascaded, 8259-compatible programmable interrupt controllers support 15 user-definable interrupt levels. Eight external interrupt requests can be mapped to any of the 15 internal IRQ inputs. The interrupt controller block includes these features: s Software-compatibility with PC/AT interrupt controllers s 15-level priority controller s Programmable interrupt modes s Individual interrupt request mask capability s Accepts requests from peripherals s Resolves priority on pending interrupts and interrupts in service s Issues interrupt request to processor s Provides interrupt vectors for interrupt service routines s Tied into the PMU for power management DRAM Controller The integrated DRAM controller provides the signals and associated timing necessary to support an external DRAM array with minimal software programming and overhead. Internal programmable registers are provided to select the DRAM type and operating mode, as well as refresh options. A wide variety of commodity DRAMs are supported, and substantial flexibility is built into the DRAM controller to optimize performance of the CPU and (on the ElanSC400 microcontroller) the internal graphics controller, which uses system DRAM for its buffers. The DRAM controller supports the following features: s 3.3-V, 70-ns DRAMs s Up to four banks s 16-bit or 32-bit banks s Up to 64 Mbyte of total memory s Self-refresh DRAMs ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet 15 The interrupt controller block is functionally compatible with the standard cascaded 8259A controller pair as implemented in the PC/AT system. The master controller drives the CPU's interrupt input signal based on the highest priority interrupt request pending at the master controller's IRQ7-IRQ0 inputs. The master IRQ2 input is configured for Cascade mode and is driven only by the slave controller's interrupt output signal. The highest pending interrupt at the slave's IRQ inputs will therefore drive the IRQ2 input of the master. The interrupt controller has programmable sources for interrupts that are controlled through extended configuration registers and, on the ElanSC400 microcontroller, through PC Card controller configuration registers. Programmable Interval Timer (PIT) The programmable interval timer (PIT) on the ElanSC400 and ElanSC410 microcontrollers is software-compatible with PC/AT 8254 system timers. The PIT provides three 16-bit counters that can be operated independently in six different modes. The PIT is generally used for timing external events, counting, and produc ing repetitive waveforms. The PIT c an be programmed to count in binary or in BCD. Real-Time Clock (RTC) T h e RT C d e s i g n e d i n t o t h e E l a n S C 4 0 0 a n d ElanSC410 microcontrollers is compatible with the MC146818A device used in PC/AT systems. The RTC consists of a time-of-day clock with alarm interrupt and a 100-year calendar. The clock/calendar has a programmable periodic interrupt, 114 bytes of static user RAM, and can be represented in either binary or BCD. The RTC includes the following features: s Counts seconds, minutes, and hours of the day s Counts days of the week, date, month, and year s 12-24 hour clock with AM and PM indication in 12-hour mode s 14 clock, status, and control registers s 114 bytes of general-purpose RAM s Three separately software-maskable and testable interrupts - Time-of-day alarm is programmable to occur from once-per-second to once-per-day - Periodic interrupts can be continued to occur at rates from 122 s to 500 ms - Update-ended interrupt provides cycle status s Dedicated power pin directly supports lithium backup battery when the rest of the chip is completely powered down (RTC-only mode) s Voltage monitor circuit checks the voltage level of the lithium backup battery and sets a bit when the battery is below specification. s Internal RTC reset signal performs a reset when power is applied to the RTC core. PC/AT Support Features The ElanSC400 and ElanSC410 microcontrollers provide all of the support functions found in the original IBM PC/AT. These include the Port B status and control bits, speaker control, CPU-core reset based on the system control processor (SCP), and A20 gate control, as well as extensions for fast CPU core reset. In addition, a CPU shutdown cycle (e.g., as a result of a triple fault) generates a CPU core reset. Bidirectional Enhanced Parallel Port (EPP) The parallel port on the ElanSC400 and ElanSC410 microcontrollers is functionally compatible with IBM PC/AT and PS/2 systems, with an added EPP mode for faster transfers. The microcontroller's parallel port interface provides all the status inputs, control outputs, and the control signals necessary for the external parallel port data buffers. The parallel port interface on both microcontrollers is shared with some of the GPIO signals and, on the ElanSC400 microcontroller, with the second PC Card socket interface. Only one of these interfaces can be enabled at one time. The parallel port interface can be configured to operate in one of three different modes of operation: s PC/AT Compatible mode: This mode provides a byte-wide forward (host-to-peripheral) channel with data and status lines used according to their original (Centronics) definitions in the IBM PC/AT. s Bidirectional mode: This mode offers byte-wide bidirectional parallel data transfers between host and peripheral, equivalent to the parallel interface on the IBM PS/2. s Enhanced Parallel Port (EPP) mode: This mode provides a byte-wide bidirectional channel controlled by the microcontroller. It provides separate address and data cycles over the eight data lines of the interface with an automatic address and data strobe for the address and data cycles, respectively. EPP mode offers wider system bandwidth and increased performance over both the PC/AT Compatible and Bidirectional modes. 16 ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet Serial Port The ElanSC400 and ElanSC410 microcontrollers include an industry-standard 16550A UART. The UART can be used to drive a standard 8-pin serial interface or a 2-pin infrared interface. The serial interface and infrared interface signals are available on the ElanSC400 and ElanSC410 microcontrollers at all times, though only one is available at any given time. The UART powers up as a 16450-compatible device. It can be switched to and from the FIFO (16550) mode under software control. In the FIFO mode, the receive and the transmit circuitry are each enhanced by separate 16-byte FIFOs to off-load the CPU from repetitive service routines. The serial port includes the following features: s Eight-pin interface: serial in, serial out, two modem control lines, and four modem status lines s Separately enabled receiver line status, receiver data, character timeout, transmitter holding register, and modem status interrupts s Baud-rate generator provides input clock divisor from 1 to 65535 to create 16x clock s 5-, 6-, 7-, or 8-bit data s Even, odd, stick, or no parity generation and checking s 1, 1-1/2 or 2 stop-bit generation s Break generation/detection (NMIs), wake-ups, or activities for the power management unit. They can also be used as I/O or memory chip selects. Infrared Port for Wireless Communication The ElanSC400 and ElanSC410 microcontrollers support infrared data transfer. This support consists of adding additional transmit and receive serializers as well as a controlling state machine and DMA interface to the internal UART. The integrated infrared port includes these features: s Low-speed mode supports all bit rates from UART, up to 115 Kbit/s s High-speed mode transfers 1.152 Mbit/s using DMA Dual PC Card Controller (ElanSC400 Microcontroller Only) The PC Card host bus adapter included on the ElanSC400 microcontroller conforms to PCMCIA Standard Release 2.1. It provides support for two sockets, each implementing the PC Card memory and I/O interfaces. The PC Card controller is not supported on the ElanSC410 microcontroller. The PC Card controller includes the following features: s ExCA-compliant, 82365-register-set compatible s 8-bit and 16-bit data bus s DMA transfers between I/O PC cards and system DRAM s Ten available memory windows, five per socket Of the two PC Card sockets supported, only one is available in all modes of operation. The second socket is multiplexed with the parallel port and GPIO features. Register set compatibility with the 82365SL PC Card Interface Controller is maintained where features are common to both controllers. Of the ten memory windows available, six are dedicated to the PC Card controller and four are shared with memory mapping system (MMS) Windows C-F. Two of the three ROM/Flash memory chip selects can be remapped to a PC Card socket via pinstrap or software control. This feature supports reprogramming of soldered down Flash memory boot devices and also simplifies testing of BIOS/XIP OS code. Keyboard Interfaces The integrated keyboard controller has the following features: s Matrix keyboard support with up to 15 rows and 8 columns s Hardware support for software emulation of the System Control Processor (SCP) emulation logic s XT keyboard interface Programmable General-Purpose Inputs and Outputs The chip supports several general-purpose I/O signals (GPIOs) that can be used on the system board. There are two classifications of GPIO available: the GPIOx signals, which are programmable as inputs or outputs only, and the GPIO_CSx signals. The GPIO_CSx signals have many programmable options. They can be configured as chip selects. As outputs, these signals are individually programmable to be High or Low for the following PMU modes: Hyper, HighSpeed, Low-Speed, Standby, and Suspend. As inputs, they can be programmed to cause System Management Interrupts (SMIs), Non-Maskable Interrupts Graphics Controller for CGA-Compatible Text and Graphics (ElanSC400 Microcontroller Only) The graphics controller included on the ElanSC400 microcontroller offers a low-cost integrated graphics solution for the mobile terminal market. Integration with the main processor and system logic affords the advan- ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet 17 tages of an integrated local-bus interface and frame and font buffers that are shared with main memory. The graphics controller is not supported on the ElanSC410 microcontroller. The graphics controller includes the following features: s Supports multiple panel resolutions s Provides internal unified memory architecture (UMA) with optional write-through caching of graphics buffers s Stores frame and font buffer data in system DRAM, eliminates extra memory chip s Provides software compatibility with Color Graphics Adapter (CGA), Monochrome Display Adapter (MDA), and Hercules Graphics Adapter (HGA) text and graphics s Supports single-scan or dual-scan monochrome LCD panels with 4-bit or 8-bit data interface s Typical panels supported include: - 640 x 200, 640 x 240, 640 x 480, 480 x 320, 480 x 240, 480 x 128, 320 x 200, 320 x 240 - Other resolutions can be supported s Supports single-scan color STN panels with 8-bit interface, same resolutions as monochrome mode s Internal local-bus interface provides high performance s Logical screen can be larger than physical window. s Supports panning and scrolling s Supports horizontal dot doubling and vertical line doubling The following MDA/CGA-compatible text mode features are supported: s 40, 64, or 80 columns with characters 16, 10, or 8 pixels wide s Variable height characters up to 32 lines s Variable width characters--8, 10, or 16 pixels s MDA Monochrome, or CGA 4 gray shades, 16 gray shades, or 16-colors s 16-Kbyte downloadable font area, relocatable on 16-Kbyte boundaries within lower 16 Mbytes of system DRAM (can be write protected) s 16-Kbyte frame buffer, relocatable on either 16-Kbyte boundaries within lower 16 Mbyte of system DRAM (CGA-compatible mode) or 32-Kbyte boundaries when the frame buffer is larger than 16 Kbyte (flat-mapped mode) The following graphics mode features are supported: s 640 x 200 1 bit-per-pixel, CGA-compatible graphics buffer memory map s 320 x 200 2 bits-per-pixel, CGA-compatible graphics buffer memory map s 640 x 480 2 bits-per-pixel, flat memory map (lower resolutions supported) s 640 x 480 1 bit-per-pixel, flat memory map s 1, 2, or 4 bits-per-pixel packed-pixel flat-mapped graphics up to 640 x 240/480 x 320 with two mapping modes: - 16-Kbyte window with bank swapping to address up to 64 Kbyte of graphics frame buffer while consuming only 16 Kbyte of DOS/Realmode CPU address space - Direct-mapped (no bank swapping) with locatable base address, up to 128-Kbyte direct addressability s Hercules Graphics mode emulation (HGA) JTAG Test Features The ElanSC400 and ElanSC410 microcontrollers provide a boundary-scan interface based on the IEEE Std 1149.1, Standard Test Access Port and BoundaryScan Architecture. The test access port provides a scan interface for testing the microcontroller and system hardware in a production environment. It contains extensions that allow a hardware-development system to control and observe the microcontroller without interposing hardware between the microcontroller and the system. System Interfaces Data Buses The ElanSC400 and ElanSC410 microcontrollers provide 32 bits of data that are divided into two separate 16-bit buses. s System Data Bus: The system (or peripheral) data bus (SD15-SD0) is always 16 bits wide and is shared between ISA, 8-bit or 16-bit ROM/Flash memory, and PC Card peripherals (ElanSC400 microcontroller only). It can be directly connected to all of these devices. In addition, these signals are the upper word of the VESA local (VL) data bus, the 32-bit DRAM interface, and the 32-bit ROM interface. s Data Bus: The D15-D0 data bus is used during 16-bit DRAM cycles. For 32-bit DRAM, VL-bus, and ROM cycles, this bus is combined with the system data bus. In other words, the data bus signals (D31-D16) are shared with the system data bus signals SD15-SD0. 18 ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet The ElanSC400 and ElanSC410 microcontrollers support the data bus configurations listed below. External transceivers or buffers can be used to isolate the buses. s 16-bit DRAM bus, 8-/16-bit ROM, 32-bit VL-bus disabled, internal graphics controller enabled/ disabled s 16-/32-bit DRAM bus, 8/16-bit ROM, 32-bit VL-bus enabled/disabled, internal graphics controller disabled s 16-/32-bit DRAM bus, 32-bit ROM, 32-bit VL-bus enabled/disabled, internal graphics controller disabled See Figure 2 on page 22 and Figure 3 on page 23 for block diagrams of example systems. The ElanSC400 and ElanSC410 microcontrollers offer flexibility in configuring the ROM and DRAM data buses for different widths. The widths (8/16/32 bits) for ROMCS0 are programmed during power-up through two pinstraps, CFG0 and CFG1. The DRAM widths (16/32 bits) are programmed through configuration registers. Up to four 16- or 32-bit banks of DRAM are supported. Two of the three ROM/Flash memory chip selects (ROMCS2-ROMCS0) can be remapped to a PC Card socket via pinstrap or software control. This feature supports reprogramming of soldered-down Flash memory boot devices and also simplifies testing of BIOS/XIP (execute in place) OS code. Address Buses There are two external address buses on the ElanSC400 and ElanSC410 microcontrollers. s System Address Bus: The SA25-SA0 system address bus outputs the physical memory or I/O port latched addresses. These addresses are used by all external peripheral devices other than main system DRAM. In addition, the system address bus is the local address bus in VL-bus mode. s DRAM Address Bus: DRAM row and column addresses are multiplexed onto the DRAM address bus (MA12-MA0). Row addresses are driven onto this bus and are valid upon the falling edge of RAS. Column addresses are driven onto this bus and are valid upon the falling edge of CAS. The SA bus is shared between the ISA bus, the VL-bus, the ROM/Flash memory controller and, on the ElanSC400 microcontroller, the PC Card controller. The ElanSC400 and ElanSC410 microcontrollers provide programmable drive strengths in the I/O buffers to accommodate loading for various system configurations. Memory Management The ElanSC400 and ElanSC410 microcontrollers manage up to nine separate physical device memory address spaces. All but the ISA memory address space can have a depth of up to 64 Mbyte each. The ISA bus memory area is limited to 16 Mbyte, as defined by ISA specifications. The microcontroller will drive all 26 address lines on ISA cycles to allow up to 64-Mbyte address space, as described in the memory management section of the ElanSC400 and ElanSC410 Microcontrollers User's Manual (order #21030)--refer to the subsection on ISA bus addressing). The nine memory spaces are: s System memory address space (DRAM) s ROM0 memory address space (ROMCS0 signal) s ROM1 memory address space (ROMCS1 signal) s ROM2 memory address space (ROMCS2 signal) s PC Card Socket A memory address spaces (common and attribute) (ElanSC400 microcontroller only) s PC Card Socket B memory address spaces (common and attribute) (ElanSC400 microcontroller only) s External ISA/VL-bus memory address space The system memory address space (DRAM) is accessible using direct-mapped CPU addresses and can also be accessed by the CPU in an indirect method using the Memory Mapping System (MMS). On the ElanSC400 microcontroller, DRAM is also accessible by the integrated graphics controller if enabled. The ROM0 address space is partially accessible via a direct mapping of the CPU address bus and partially accessible via the MMS. The ROM1 and ROM2 address spaces are only accessible indirectly using the MMS. On the ElanSC400 microcontroller, the PC Card address spaces are accessed through a separate, 82365SL-compatible address mapping system. The ISA/VL-bus address space is accessible as a direct mapping of the CPU address bus. ISA memory cycles are generated when the CPU generates a memory cycle that is not detected as an access to any other memory space. An ISA bus memory cycle can also be generated if the CPU generates a memory address that resides in the ISA overlapping memory region window. This window can be defined to overlay any system memory region below 16 Mbyte. ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet 19 ISA Bus Interface For External ISA Peripherals The ISA interface consists of a subset of ISA-compatible bus signals, allowing for the connection of 8- or 16-bit devices supporting ISA-compatible I/O, memory, and DMA cycles. The following features are supported: s 8.2944-MHz maximum bus clock speed s Programmable DMA clock speed up to 16 MHz s 8-bit and 16-bit ISA I/O and memory cycles (ISA memory is non-cacheable) s Direct connection to 3- or 5-volt peripherals Eight programmable IRQ input signals are available. These interrupts can be routed via software to any available PC/AT-compatible interrupt channel. Two programmable DMA channels are available for external DMA peripherals. These DMA channels can be routed to software to any available ISA DMA channel. VESA Local (VL) Bus Interface Supports 32-Bit Memory and I/O Targets The VESA local (VL) bus controller provides the signals and associated timing necessary to support a single VESA compliant VL-bus target. Multiple VL-bus targets can be supported using external circuitry to allow multiple VL devices to share the VL_LDEV signal. This allows the ElanSC400 and ElanSC410 microcontrollers to operate as a normal VL-bus motherboard controller, in accordance with the VL-Bus Standard 2.0. On the ElanSC400 microcontroller, the VL-bus is available only when the internal graphics controller is disabled. The microcontroller's VL-bus controller includes the following features: s 33-MHz operation at 3.3 V s 32-bit data bus s Burst-mode transfers s Register control of local bus reset VESA bus mastering and DMA transfers to and from the VL-bus target are not supported. VL memory is non-cacheable. SYSTEM CONSIDERATIONS Figure 1 shows the ElanSC400 microcontroller as it might be used in a minimal system design. Figure 2 and Figure 3 show more complex system designs for each microcontroller and the features that are traded for others because of pin multiplexing. s The ElanSC400 and ElanSC410 microcontrollers support a maximum of 4 banks of 32-bit DRAM, but because the RAS and CAS signals for the high word and for banks 2 and 3 are traded for keyboard row signals, the minimum system would have one or two banks of DRAM (either Bank 0 or Bank 1) populated with 16-bit DRAMs. The MA12 signal for asymmetrical support is also traded with a keyboard row signal. s Because the VL-bus and the graphics controller share control signals on the ElanSC400 microcontroller, use of the internal graphics controller is traded with having an external VL-bus on that microcontroller. s If either 32-bit DRAMs, 32-bit ROMs, or the VL-bus is enabled, the internal graphics controller on the ElanSC400 microcontroller is unavailable because of internal design constraints. s The ElanSC400 and ElanSC410 microcontrollers provide an absolute minimum of dedicated ISA control signals. Any additional ISA controls are traded with GPIOs or keyboard rows and columns. s The SD buffer shares control signals with some of the GPIOs. This buffer controls the high word of the D data bus (D31-D16). Note that using the SD buffer is optional. The high word of the D data bus can be hooked up directly to devices that want the SD data bus (SD15-SD0). Buffering aids in voltage translation or isolation for heavy loading. s The R32BFOE signal buffers the high word of the D data bus (D31-D16) for 32-bit ROMs. The control signal associated with the ROM32 buffer is shared with a keyboard row. s On the ElanSC400 microcontroller, the parallel port is traded for PC Card Socket B. It requires an external buffer and latch. s The serial and infrared ports share the same internal UART. Real-time switching between the two is supported; however, only one port is available at any given time. s ROMCS2 is not connected to a dedicated pin. Software can enable and map it to any of the 15 GPIO_CS signals. 20 ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet Bank 0 Bank 1 Ctrl Low Word D15-D0 MA11-MA0 Matrix Keyboard Row Conn Column Conn Ctrl DRAM DRAM LCD ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet 21 Figure 1. Typical Mobile Terminal Design 32-kHz Crystal Loop Filters Backup Battery Pwr Conn Battery Ctrl Power Supply MA Low D Ctrl Rows Columns LCD SA25-SA0 GPIO_CS12-GPIO_CS0 High D SD15-SD0 ElanSC400 Microcontroller Ctrl PC Card A Ctrl PC Card B Ctrl Serial Infrared SD SA SD SA Ctrl Ctrl SA25-SA1 SD15-SD0 Ctrl BIOS/OS Flash/ ROM Serial Translator Serial Conn Speaker Infrared PC Card Socket B PC Card Socket A 22 Bank 0 High Word Bank 1 Bank 2 Bank 3 DRAM DRAM DRAM DRAM Low Word DRAM DRAM DRAM DRAM Ctrl MA12 Keyboard Figure 2. System Diagram with Trade-offs--ElanSC400 Microcontroller High D Low D Ctrl MA Low D Ctrl Rows Columns SA ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet VL Bus Device ElanSC400 Microcontroller LCD LCD Conn Ctrl SD Buffer 32-kHz Crystal High D Ctrl SA Ctrl PC Card A Ctrl PC Card B Ctrl Serial Infrared Ctrl SD Ctrl SD ROM32 Buffer SA Ctrl Ctrl SA Ctrl Ctrl ISA Bus Device Loop Filters SD Ctrl Ctrl SD SA SD Low D SD SA BIOS/ OS/ Apps Flash ROM Backup Battery Battery Serial Translator Power Supply Infrared Serial Conn Buffer Latch PC Card Socket B PC Card Socket A Parallel Port Connector Notes: A dashed box indicates a feature that is optional or is traded for another. Bank 0 High Word Bank 1 Bank 2 Bank 3 DRAM DRAM DRAM DRAM Low Word DRAM DRAM DRAM DRAM Ctrl MA12 Keyboard Figure 3. System Design with Trade-offs--ElanSC410 Microcontroller High D Low D DRAM Ctrl Rows Columns Ctrl SA ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet 23 MA Low D VL Bus Device ElanSC410 Microcontroller VL-Bus Ctrl Ctrl SD Buffer 32-kHz Crystal High D ISA Ctrl SD Ctrl SD ROM32 Buffer SA Ctrl Ctrl SA Ctrl Low D SD ISA Bus Device Loop Filters SA ROM Ctrl Parallel Ctrl Serial IrDA Ctrl Ctrl BIOS/ OS/ Apps Flash ROM Backup Battery Serial Translator Power Supply Infrared Serial Conn Buffer and Latch Notes: Parallel Port Connector A dashed box indicates a feature that is optional or is traded for another. CONNECTION DIAGRAM--ElanSC400 AND ElanSC410 MICROCONTROLLERS 292 Ball Grid Array (BGA) Package Top View (from component side looking through to bottom) 1 A B C D E F G H J K L M N P R T U V W Y 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 A B C D E F G H J K L M N P R T U V W Y 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 24 ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet PIN DESIGNATIONS This section identifies the pins of the ElanSC400 and ElanSC410 microcontrollers and lists the signals associated with each pin. Several different tables are included in this section. s The Pin Designations (Pin Number)--ElanSC400 Microcontroller table beginning on page 26 lists the ElanSC400 microcontroller signals sorted by pin number. The Pin Designations (Pin Number)--ElanSC410 Mi c r oc o nt r ol l er t ab l e o n pa ge 33 l i st s th e ElanSC410 microcontroller signals sorted by pin number. Along with the Connection Diagram on page 24, these tables can be used to associate the complete pin name (including all multiplexed functions) with the physical pin on the BGA package. s The Pin Designations (Pin Name)--ElanSC400 Mi c r oc o nt r ol l er t ab l e o n pa ge 29 l i st s th e ElanSC400 microcontroller signals sorted in alphabetical order. The Pin Designations (Pin Name)--ElanSC410 Mi c r oc o nt r ol l er t ab l e o n pa ge 36 l i st s th e ElanSC410 microcontroller signals sorted in alphabetical order. All multiplexed signals are included in these lists. Note that these tables should not be used to determine primary and secondary functions for multiplexed pins because the ordering was changed to alphabetize every function. Please refer to the Pin Designations (Pin Number) table or the Pin State tables for the definitive listing of primary and secondary functions in the correct order for each pin. s The Pin State tables beginning on page 42, which group pins alphabetically by function, show pin states during reset, normal operation, and Suspend mode, along with output drive strength, maximum load, supply source, and power-down groups. s The Signal Description table beginning on page 62 includes complete pin descriptions in alphabetical order by function. s The table beginning on page 70 clarifies the configuration options for those pins having multiple functions. Pin Naming The Signal Name column in the Pin Designation tables beginning on page 26 and in the Pin State tables beginning on page 40 is decoded as follows: NAME1/NAME2 {NAME3} [NAME4] [[NAME5]] NAME1 This is the only function for the pin. NAME1/NAME2 The slash separates two functions that are available on the pin at the same time (i.e., at different times in the same design the pin is used for different functions). {NAME3} The name in braces is the pin function during a hardware reset. [NAME4] The name in square brackets is the alternative function for the pin, selected by firmware configuration. Only one function is available for each configuration. [[NAME5]] The name inside double square brackets is the alternate function for the pin, selected by a hardware configuration pin state at power-on reset. This does not apply to [[BNDSCN_TCK]], [[BNDSCN_TMS]], [[BNDSCN_TDI]], and [[BNDSCN_TDO]]. These four alternate functions are enabled by the BNDSCN_EN signal. Only one function is available for each configuration. PIN CHANGES FOR THE ElanSC410 MICROCONTROLLER The following signals supported on the ElanSC400 microcontroller are not available on the ElanSC410 microcontroller. s Configuration signal: CFG2 s PC Card controller signals: MCEL_A, MCEL_B, MCEH_A, MCEH_B, RST_A, RST_B, REG_A, REG_B, CD_A, CD_B, CD_A2, RDY_A, RDY_B, BVD1_A, BVD1_B, BVD2_A, BVD2_B, WP_A, WP_B, WAIT_AB, OE, WE, ICDIR, PCMA_VCC, PCMA_VPP1, PCMA_VPP2, PCMB_VCC, PCMB_VPP1, PCMB_VPP2 s Graphics controller signals: LCDD7-LCDD0, M, LC, SCK, FRM, LVEE, LVDD s Loop filter signal: LF_VID ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet 25 PIN DESIGNATIONS (Pin Number)--ElanSC400 Microcontroller Pin No. A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 Signal Name KBD_COL5/PIRQ6 KBD_COL2/PIRQ3 KBD_ROW13 [[R32BFOE]] D15 D12 D9 D7 VCC D4 D1 MWE MA2 {CFG2} VCC MA5 MA8 MA11 CASH1 VCC LVDD [VL_BLAST] LVEE [VL_BRDY] VCC KBD_COL6/PIRQ7 KBD_COL3/PIRQ4 VCC D14 D11 D8 D5 D3 D0 MA1 {CFG1} MA3 {CFG3} MA6 MA9 CASL0 VCC KBD_ROW6 [MA12] KBD_ROW3 [CASH3] Pin No. B19 B20 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 Signal Name KBD_ROW0 [CASL2] LCDD0 [VL_RST] KBD_ROW11 [SBHE] KBD_ROW8 [PDRQ1] KBD_COL4/PIRQ5 GPIO_CS4 [[DBUFOE]] KBD_COL7 D13 D10 D6 D2 MA0 {CFG0} MA4 MA7 MA10 CASL1 RAS0 KBD_ROW5 [RAS3] KBD_ROW2 [CASH2] GPIO_CS2 [[DBUFRDL]] LCDD1 [VL_ADS] LCDD3 [VL_M/IO] KBD_COL1 [XT_CLK] KBD_ROW10 [BALE] KBD_ROW7 [PDACK1] GND GND GND GND GND GND GND GND GND CASH0 RAS1 KBD_ROW4 [RAS2] KBD_ROW1 [CASL3] Pin No. D17 D18 D19 D20 E1 E2 E3 E4 E17 E18 E19 E20 F1 F2 F3 F4 F17 F18 F19 F20 G1 G2 G3 G4 G17 G18 G19 G20 H1 H2 H3 H4 H8 H9 H10 H11 H12 H13 Signal Name GPIO_CS3 [[DBUFRDH]] LCDD2 [VL_W/R] LCDD4 [VL_LRDY] LCDD7 [VL_BE3] VCC KBD_COL0 [XT_DATA] KBD_ROW9 [PIRQ2] GND VCC LCDD5 [VL_D/C] FRM [VL_LCLK] LC [VL_BE1] SD4 [D20] SD1 [D17] KBD_ROW12 [MCS16] GND LCDD6 [VL_LDEV] M [VL_BE2] SCK [VL_BE0] SA24 SD6 [D22] SD3 [D19] SD0 [D16] GND VCC GPIO20 [CD_A2] SA22 SA21 VCC SD5 [D21] SD2 [D18] GND GND GND GND GND GND GND 26 ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet PIN DESIGNATIONS (Pin Number)--ElanSC400 Microcontroller (Continued) Pin No. H17 H18 H19 H20 J1 J2 J3 J4 J8 J9 J10 J11 J12 J13 J17 J18 J19 J20 K1 K2 K3 K4 K8 K9 K10 K11 K12 K13 K17 K18 K19 K20 L1 L2 L3 L4 L8 L9 Signal Name SA25 SA23 SA20 SA18 SD10 [D26] SD7 [D23] VCC GND GND GND GND GND GND GND VCC SA19 SA17 SA14 SD11 [D27] SD9 [D25] SD8 [D24] VCC_CPU GND GND GND GND GND GND SA16 SA15 SA13 SA12 SD12 [D28] SD13 [D29] SD15 [D31] VCC_CPU GND GND Pin No. L10 L11 L12 L13 L17 L18 L19 L20 M1 M2 M3 M4 M8 M9 M10 M11 M12 M13 M17 M18 M19 M20 N1 N2 N3 N4 N8 N9 N10 N11 N12 N13 N17 N18 N19 N20 P1 P2 Signal Name GND GND GND GND VCC SA10 SA9 SA11 VCC REG_A [[BDNSCN_TDO]] ICDIR VCC_CPU GND GND GND GND GND GND VCC SA7 VCC SA8 SD14 [D30] WE MCEH_A [[BNDSCN_TMS]] VCC_CPU GND GND GND GND GND GND VCC SA3 SA5 SA6 OE MCEL_A [[BNDSCN_TCK]] Pin No. P3 P4 P17 P18 P19 P20 R1 R2 R3 R4 R17 R18 R19 R20 T1 T2 T3 T4 T17 T18 T19 T20 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 Signal Name RDY_A VCC_CPU VCC VCC SA1 SA4 RST_A [[BNDSCN_TDI]] CD_A BVD2_A VCC_CPU GND ROMCS0 IOW SA2 VCC WP_A GPIO22 [PPOEN] VCC_CPU GND MEMW ROMCS1 SA0 WAIT_AB GPIO25 [ACK] [BVD1_B] GPIO24 [BUSY] [BVD2_B] GPIO23 [SLCT] [WP_B] GND GND GND GND GND GND GND GND GND GND GND GND ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet 27 PIN DESIGNATIONS (Pin Number)--ElanSC400 Microcontroller (Continued) Pin No. U17 U18 U19 U20 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 Signal Name GND VCC ROMWR IOR BVD1_A GPIO31 [STRB] [MCEL_B] GPIO21 [PPDWE] GPIO27 [ERROR] [CD_B] LF_HS BBATSEN SPKR SIROUT DCD CTS RIN RSTDRV VCC GPIO19 [LBL2] GPIO16 [PCMB_VCC] GPIO_CS13 [PCMA_VCC] GPIO_CS10 [AEN] GPIO_CS6 [IOCHRDY] Pin No. V19 V20 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 Signal Name GPIO_CS0 ROMRD GPIO30 [AFDT] [MCEH_B] GPIO26 [PE] [RDY_B] GPIO29 [SLCTIN] [RST_B] LF_LS LF_VID VCC_A VCC_RTC RTS VCC DSR SIN ACIN BL2 BL0 [CLK_IO] GPIO17 [PCMB_VPP1] GPIO_CS14 [PCMA_VPP1] GPIO_CS11 [PDACK0] GPIO_CS8 [PIRQ0] GPIO_CS5 [IOCS16] MEMR Pin No. Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Signal Name VCC GPIO28 [INIT] [REG_B] LF_INT 32KXTAL2 GND_ANALOG 32KXTAL1 RESET DTR SIRIN SOUT BNDSCN_EN SUS_RES/KBD_ROW14 BL1 GPIO18 [PCMB_VPP2] GPIO15 [PCMA_VPP2] VCC GPIO_CS12 [PDRQ0] GPIO_CS9 [TC] GPIO_CS7 [PIRQ1] GPIO_CS1 28 ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet PIN DESIGNATIONS (Pin Name)--ElanSC400 Microcontroller Signal Name ACIN [ACK] [BVD1_B] GPIO25 [AEN] GPIO_CS10 [AFDT] [MCEH_B] GPIO30 [BALE] KBD_ROW10 BBATSEN BL0 [CLK_IO] BL1 BL2 BNDSCN_EN [[BNDSCN_TCK]] MCEL_A [[BNDSCN_TDI]] RST_A [[BNDSCN_TDO]] REG_A [[BNDSCN_TMS]] MCEH_A [BUSY] [BVD2_B] GPIO24 BVD1_A [BVD1_B] GPIO25 [ACK] BVD2_A [BVD2_B] GPIO24 [BUSY] CASH0 CASH1 [CASH2] KBD_ROW2 [CASH3] KBD_ROW3 CASL0 CASL1 [CASL2] KBD_ROW0 [CASL3] KBD_ROW1 CD_A [CD_A2] GPIO20 [CD_B] GPIO27 [ERROR] {CFG0} MA0 {CFG1} MA1 {CFG2} MA2 {CFG3} MA3 [CLK_IO] BL0 CTS D0 D1 Pin No. W12 U2 V17 W1 D2 V6 W14 Y13 W13 Y11 P2 R1 M2 N3 U3 V1 U2 R3 U3 D13 A17 C17 B18 B15 C14 B19 D16 R2 G18 V4 C10 B11 A12 B12 W14 V10 B10 A10 Signal Name D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 [D16] SD0 [D17] SD1 [D18] SD2 [D19] SD3 [D20] SD4 [D21] SD5 [D22] SD6 [D23] SD7 [D24] SD8 [D25] SD9 [D26] SD10 [D27] SD11 [D28] SD12 [D29] SD13 [D30] SD14 [D31] SD15 [[DBUFOE]] GPIO_CS4 [[DBUFRDH]] GPIO_CS3 [[DBUFRDL]] GPIO_CS2 DCD DSR DTR [ERROR] [CD_B] GPIO27 FRM [VL_LCLK] Pin No. C9 B9 A9 B8 C8 A7 B7 A6 C7 B6 A5 C6 B5 A4 G3 F2 H3 G2 F1 H2 G1 J2 K3 K2 J1 K1 L1 L2 N1 L3 C4 D17 C18 V9 W10 Y8 V4 E19 Signal Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin No. D4 D5 D6 D7 D8 D9 D10 D11 D12 E4 F4 G4 H4 H8 H9 H10 H11 H12 H13 J4 J8 J9 J10 J11 J12 J13 K8 K9 K10 K11 K12 K13 L8 L9 L10 L11 L12 L13 ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet 29 PIN DESIGNATIONS (Pin Name)--ElanSC400 Microcontroller (Continued) Signal Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND_ANALOG GPIO_CS0 GPIO_CS1 GPIO_CS2 [[DBUFRDL]] GPIO_CS3 [[DBUFRDH]] GPIO_CS4 [[DBUFOE]] GPIO_CS5 [IOCS16] GPIO_CS6 [IOCHRDY] GPIO_CS7 [PIRQ1] GPIO_CS8 [PIRQ0] GPIO_CS9 [TC] Pin No. M8 M9 M10 M11 M12 M13 N8 N9 N10 N11 N12 N13 R17 T17 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 Y5 V19 Y20 C18 D17 C4 W19 V18 Y19 W18 Y18 Signal Name GPIO_CS10 [AEN] GPIO_CS11 [PDACK0] GPIO_CS12 [PDRQ0] GPIO_CS13 [PCMA_VCC] GPIO_CS14 [PCMA_VPP1] GPIO15 [PCMA_VPP2] GPIO16 [PCMB_VCC] GPIO17 [PCMB_VPP1] GPIO18 [PCMB_VPP2] GPIO19 [LBL2] GPIO20 [CD_A2] GPIO21 [PPDWE] GPIO22 [PPOEN] GPIO23 [SLCT] [WP_B] GPIO24 [BUSY] [BVD2_B] GPIO25 [ACK] [BVD1_B] GPIO26 [PE] [RDY_B] GPIO27 [ERROR] [CD_B] GPIO28 [INIT] [REG_B] GPIO29 [SLCTIN] [RST_B] GPIO30 [AFDT] [MCEH_B] GPIO31 [STRB] [MCEL_B] ICDIR [INIT] [REG_B] GPIO28 [IOCHRDY] GPIO_CS6 [IOCS16] GPIO_CS5 IOR IOW 32KXTAL1 32KXTAL2 KBD_COL0 [XT_DATA] KBD_COL1 [XT_CLK] KBD_COL2/PIRQ3 KBD_COL3/PIRQ4 KBD_COL4/PIRQ5 KBD_COL5/PIRQ6 KBD_COL6/PIRQ7 KBD_COL7 Pin No. V17 W17 Y17 V16 W16 Y15 V15 W15 Y14 V14 G18 V3 T3 U4 U3 U2 W2 V4 Y2 W3 W1 V2 M3 Y2 V18 W19 U20 R19 Y6 Y4 E2 D1 A2 B3 C3 A1 B2 C5 Signal Name KBD_ROW0 [CASL2] KBD_ROW1 [CASL3] KBD_ROW2 [CASH2] KBD_ROW3 [CASH3] KBD_ROW4 [RAS2] KBD_ROW5 [RAS3] KBD_ROW6 [MA12] KBD_ROW7 [PDACK1] KBD_ROW8 [PDRQ1] KBD_ROW9 [PIRQ2] KBD_ROW10 [BALE] KBD_ROW11 [SBHE] KBD_ROW12 [MCS16] KBD_ROW13 [[R32BFOE]] KBD_ROW14 / SUS_RES [LBL2] GPIO19 LC [VL_BE1] LCDD0 [VL_RST] LCDD1 [VL_ADS] LCDD2 [VL_W/R] LCDD3 [VL_M/IO] LCDD4 [VL_LRDY] LCDD5 [VL_D/C] LCDD6 [VL_LDEV] LCDD7 [VL_BE3] LF_HS LF_INT LF_LS LF_VID LVDD [VL_BLAST] LVEE [VL_BRDY] M [VL_BE2] MA0 {CFG0} MA1 {CFG1} MA2 {CFG2} MA3 {CFG3} MA4 MA5 Pin No. B19 D16 C17 B18 D15 C16 B17 D3 C2 E3 D2 C1 F3 A3 Y12 V14 E20 B20 C19 D18 C20 D19 E18 F17 D20 V5 Y3 W4 W5 A19 A20 F18 C10 B11 A12 B12 C11 A14 30 ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet PIN DESIGNATIONS (Pin Name)--ElanSC400 Microcontroller (Continued) Signal Name MA6 MA7 MA8 MA9 MA10 MA11 [MA12] KBD_ROW6 MCEH_A [[BNDSCN_TMS]] [MCEH_B] GPIO30 [AFDT] MCEL_A [[BNDSCN_TCK]] [MCEL_B] GPIO31 [STRB] [MCS16] KBD_ROW12 MEMR MEMW MWE OE [PCMA_VCC] GPIO_CS13 [PCMA_VPP1] GPIO_CS14 [PCMA_VPP2] GPIO15 [PCMB_VCC] GPIO16 [PCMB_VPP1] GPIO17 [PCMB_VPP2] GPIO18 [PDACK0] GPIO_CS11 [PDACK1] KBD_ROW7 [PDRQ0] GPIO_CS12 [PDRQ1] KBD_ROW8 [PE] [RDY_B] GPIO26 [PIRQ0] GPIO_CS8 [PIRQ1] GPIO_CS7 [PIRQ2] KBD_ROW9 PIRQ3/KBD_COL2 PIRQ4/KBD_COL3 PIRQ5/KBD_COL4 PIRQ6/KBD_COL5 PIRQ7/KBD_COL6 [PPDWE] GPIO21 [PPOEN] GPIO22 [[R32BFOE]] KBD_ROW13 Pin No. B13 C12 A15 B14 C13 A16 B17 N3 W1 P2 V2 F3 W20 T18 A11 P1 V16 W16 Y15 V15 W15 Y14 W17 D3 Y17 C2 W2 W18 Y19 E3 A2 B3 C3 A1 B2 V3 T3 A3 Signal Name RAS0 RAS1 [RAS2] KBD_ROW4 [RAS3] KBD_ROW5 RDY_A [RDY_B] GPIO26 [PE] REG_A [[BNDSCN_TDO]] [REG_B] GPIO28 [INIT] RESET RIN ROMCS0 ROMCS1 ROMRD ROMWR RST_A [[BNDSCN_TDI]] [RST_B] GPIO29 [SLCTIN] RSTDRV RTS SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 Pin No. C15 D14 D15 C16 P3 W2 M2 Y2 Y7 V11 R18 T19 V20 U19 R1 W3 V12 W8 T20 P19 R20 N18 P20 N19 N20 M18 M20 L19 L18 L20 K20 K19 J20 K18 K17 J19 H20 J18 Signal Name SA20 SA21 SA22 SA23 SA24 SA25 [SBHE] KBD_ROW11 SCK [VL_BE0] SD0 [D16] SD1 [D17] SD2 [D18] SD3 [D19] SD4 [D20] SD5 [D21] SD6 [D22] SD7 [D23] SD8 [D24] SD9 [D25] SD10 [D26] SD11 [D27] SD12 [D28] SD13 [D29] SD14 [D30] SD15 [D31] SIN SIRIN SIROUT [SLCT] [WP_B] GPIO23 [SLCTIN] [RST_B] GPIO29 SOUT SPKR [STRB] [MCEL_B] GPIO31 SUS_RES/KBD_ROW14 [TC] GPIO_CS9 VCC VCC VCC VCC Pin No. H19 G20 G19 H18 F20 H17 C1 F19 G3 F2 H3 G2 F1 H2 G1 J2 K3 K2 J1 K1 L1 L2 N1 L3 W11 Y9 V8 U4 W3 Y10 V7 V2 Y12 Y18 A8 A13 A18 B1 ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet 31 PIN DESIGNATIONS (Pin Name)--ElanSC400 Microcontroller (Continued) Signal Name VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Pin No. B4 B16 E1 E17 G17 H1 J3 J17 L17 M1 M17 M19 N17 P17 P18 T1 U18 Signal Name VCC VCC VCC VCC VCC_A VCC_CPU VCC_CPU VCC_CPU VCC_CPU VCC_CPU VCC_CPU VCC_CPU VCC_RTC [VL_ADS] LCDD1 [VL_BE0] SCK [VL_BE1] LC [VL_BE2] M Pin No. V13 W9 Y1 Y16 W6 K4 L4 M4 N4 P4 R4 T4 W7 C19 F19 E20 F18 Signal Name [VL_BE3] LCDD7 [VL_BLAST] LVDD [VL_BRDY] LVEE [VL_D/C] LCDD5 [VL_LCLK] FRM [VL_LDEV] LCDD6 [VL_LRDY] LCDD4 [VL_M/IO] LCDD3 [VL_RST] LCDD0 [VL_W/R] LCDD2 WAIT_AB WE WP_A [WP_B] GPIO23 [SLCT] [XT_CLK] KBD_COL1 [XT_DATA] KBD_COL0 Pin No. D20 A19 A20 E18 E19 F17 D19 C20 B20 D18 U1 N2 T2 U4 D1 E2 32 ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet PIN DESIGNATIONS (Pin Number)--ElanSC410 MICROCONTROLLER Pin No. A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 Signal Name KBD_COL5/PIRQ6 KBD_COL2/PIRQ3 KBD_ROW13 [[R32BFOE]] D15 D12 D9 D7 VCC D4 D1 MWE MA2 VCC MA5 MA8 MA11 CASH1 VCC VL_BLAST VL_BRDY VCC KBD_COL6/PIRQ7 KBD_COL3/PIRQ4 VCC D14 D11 D8 D5 D3 D0 MA1 {CFG1} MA3 {CFG3} MA6 MA9 CASL0 VCC KBD_ROW6 [MA12] KBD_ROW3 [CASH3] Pin No. B19 B20 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 Signal Name KBD_ROW0 [CASL2] VL_RST KBD_ROW11 [SBHE] KBD_ROW8 [PDRQ1] KBD_COL4/PIRQ5 GPIO_CS4 [[DBUFOE]] KBD_COL7 D13 D10 D6 D2 MA0 {CFG0} MA4 MA7 MA10 CASL1 RAS0 KBD_ROW5 [RAS3] KBD_ROW2 [CASH2] GPIO_CS2 [[DBUFRDL]] VL_ADS VL_M/IO KBD_COL1 [XT_CLK] KBD_ROW10 [BALE] KBD_ROW7 [PDACK1] GND GND GND GND GND GND GND GND GND CASH0 RAS1 KBD_ROW4 [RAS2] KBD_ROW1 [CASL3] Pin No. D17 D18 D19 D20 E1 E2 E3 E4 E17 E18 E19 E20 F1 F2 F3 F4 F17 F18 F19 F20 G1 G2 G3 G4 G17 G18 G19 G20 H1 H2 H3 H4 H8 H9 H10 H11 H12 H13 Signal Name GPIO_CS3 [[DBUFRDH]] VL_W/R VL_LRDY VL_BE3 VCC KBD_COL0 [XT_DATA] KBD_ROW9 [PIRQ2] GND VCC VL_D/C VL_LCLK VL_BE1 SD4 [D20] SD1 [D17] KBD_ROW12 [MCS16] GND VL_LDEV VL_BE2 VL_BE0 SA24 SD6 [D22] SD3 [D19] SD0 [D16] GND VCC GPIO20 SA22 SA21 VCC SD5 [D21] SD2 [D18] GND GND GND GND GND GND GND ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet 33 PIN DESIGNATIONS (Pin Number)--ElanSC410 MICROCONTROLLER (Continued) Pin No. H17 H18 H19 H20 J1 J2 J3 J4 J8 J9 J10 J11 J12 J13 J17 J18 J19 J20 K1 K2 K3 K4 K8 K9 K10 K11 K12 K13 K17 K18 K19 K20 L1 L2 L3 L4 L8 L9 Signal Name SA25 SA23 SA20 SA18 SD10 [D26] SD7 [D23] VCC GND GND GND GND GND GND GND VCC SA19 SA17 SA14 SD11 [D27] SD9 [D25] SD8 [D24] VCC_CPU GND GND GND GND GND GND SA16 SA15 SA13 SA12 SD12 [D28] SD13 [D29] SD15 [D31] VCC_CPU GND GND Pin No. L10 L11 L12 L13 L17 L18 L19 L20 M1 M2 M3 M4 M8 M9 M10 M11 M12 M13 M17 M18 M19 M20 N1 N2 N3 N4 N8 N9 N10 N11 N12 N13 N17 N18 N19 N20 P1 P2 Signal Name GND GND GND GND VCC SA10 SA9 SA11 VCC [[BNDSCN_TDO]] Reserved VCC_CPU GND GND GND GND GND GND VCC SA7 VCC SA8 SD14 [D30] Reserved [[BNDSCN_TMS]] VCC_CPU GND GND GND GND GND GND VCC SA3 SA5 SA6 Reserved [[BNDSCN_TCK]] Pin No. P3 P4 P17 P18 P19 P20 R1 R2 R3 R4 R17 R18 R19 R20 T1 T2 T3 T4 T17 T18 T19 T20 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 Signal Name Reserved VCC_CPU VCC VCC SA1 SA4 [[BNDSCN_TDI]] Reserved Reserved VCC_CPU GND ROMCS0 IOW SA2 VCC Reserved GPIO22 [PPOEN] VCC_CPU GND MEMW ROMCS1 SA0 Reserved GPIO25 [ACK] GPIO24 [BUSY] GPIO23 [SLCT] GND GND GND GND GND GND GND GND GND GND GND GND 34 ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet PIN DESIGNATIONS (Pin Number)--ElanSC410 MICROCONTROLLER (Continued) Pin No. U17 U18 U19 U20 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 Signal Name GND VCC ROMWR IOR Reserved GPIO31 [STRB] GPIO21 [PPDWE] GPIO27 [ERROR] LF_HS BBATSEN SPKR SIROUT DCD CTS RIN RSTDRV VCC GPIO19 [LBL2] GPIO16 GPIO_CS13 GPIO_CS10 [AEN] GPIO_CS6 [IOCHRDY] Pin No. V19 V20 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 Signal Name GPIO_CS0 ROMRD GPIO30 [AFDT] GPIO26 [PE] GPIO29 [SLCTIN] LF_LS Reserved VCC_A VCC_RTC RTS VCC DSR SIN ACIN BL2 BL0 [CLK_IO] GPIO17 GPIO_CS14 GPIO_CS11 [PDACK0] GPIO_CS8 [PIRQ0] GPIO_CS5 [IOCS16] MEMR Pin No. Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Signal Name VCC GPIO28 [INIT] LF_INT 32KXTAL2 GND_ANALOG 32KXTAL1 RESET DTR SIRIN SOUT BNDSCN_EN SUS_RES/KBD_ROW14 BL1 GPIO18 GPIO15 VCC GPIO_CS12 [PDRQ0] GPIO_CS9 [TC] GPIO_CS7 [PIRQ1] GPIO_CS1 ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet 35 PIN DESIGNATIONS (Pin Name)--ElanSC410 MICROCONTROLLER Signal Name ACIN [ACK] GPIO25 [AEN] GPIO_CS10 [AFDT] GPIO30 [BALE] KBD_ROW10 BBATSEN BL0 [CLK_IO] BL1 BL2 BNDSCN_EN [[BNDSCN_TCK]] [[BNDSCN_TDI]] [[BNDSCN_TDO]] [[BNDSCN_TMS]] [BUSY] GPIO24 CASH0 CASH1 [CASH2] KBD_ROW2 [CASH3] KBD_ROW3 CASL0 CASL1 [CASL2] KBD_ROW0 [CASL3] KBD_ROW1 {CFG0} MA0 {CFG1} MA1 {CFG3} MA3 [CLK_IO] BL0 CTS D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 Pin No. W12 U2 V17 W1 D2 V6 W14 Y13 W13 Y11 P2 R1 M2 N3 U3 D13 A17 C17 B18 B15 C14 B19 D16 C10 B11 B12 W14 V10 B10 A10 C9 B9 A9 B8 C8 A7 B7 A6 Signal Name D10 D11 D12 D13 D14 D15 [D16] SD0 [D17] SD1 [D18] SD2 [D19] SD3 [D20] SD4 [D21] SD5 [D22] SD6 [D23] SD7 [D24] SD8 [D25] SD9 [D26] SD10 [D27] SD11 [D28] SD12 [D29] SD13 [D30] SD14 [D31] SD15 [[DBUFOE]] GPIO_CS4 [[DBUFRDH]] GPIO_CS3 [[DBUFRDL]] GPIO_CS2 DCD DSR DTR [ERROR] GPIO27 GND GND GND GND GND GND GND GND GND Pin No. C7 B6 A5 C6 B5 A4 G3 F2 H3 G2 F1 H2 G1 J2 K3 K2 J1 K1 L1 L2 N1 L3 C4 D17 C18 V9 W10 Y8 V4 D4 D5 D6 D7 D8 D9 D10 D11 D12 Signal Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin No. E4 F4 G4 H4 H8 H9 H10 H11 H12 H13 J4 J8 J9 J10 J11 J12 J13 K8 K9 K10 K11 K12 K13 L8 L9 L10 L11 L12 L13 M8 M9 M10 M11 M12 M13 N8 N9 N10 36 ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet PIN DESIGNATIONS (Pin Name)--ElanSC410 MICROCONTROLLER (Continued) Signal Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND_ANALOG GPIO_CS0 GPIO_CS1 GPIO_CS2 [[DBUFRDL]] GPIO_CS3 [[DBUFRDH]] GPIO_CS4 [[DBUFOE]] GPIO_CS5 [IOCS16] GPIO_CS6 [IOCHRDY] GPIO_CS7 [PIRQ1] GPIO_CS8 [PIRQ0] GPIO_CS9 [TC] GPIO_CS10 [AEN] GPIO_CS11 [PDACK0] GPIO_CS12 [PDRQ0] GPIO_CS13 GPIO_CS14 GPIO15 GPIO16 GPIO17 GPIO18 Pin No. N11 N12 N13 R17 T17 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 Y5 V19 Y20 C18 D17 C4 W19 V18 Y19 W18 Y18 V17 W17 Y17 V16 W16 Y15 V15 W15 Y14 Signal Name GPIO19 [LBL2] GPIO20 GPIO21 [PPDWE] GPIO22 [PPOEN] GPIO23 [SLCT] GPIO24 [BUSY] GPIO25 [ACK] GPIO26 [PE] GPIO27 [ERROR] GPIO28 [INIT] GPIO29 [SLCTIN] GPIO30 [AFDT] GPIO31 [STRB] [INIT] GPIO28 [IOCHRDY] GPIO_CS6 [IOCS16] GPIO_CS5 IOR IOW 32KXTAL1 32KXTAL2 KBD_COL0 [XT_DATA] KBD_COL1 [XT_CLK] KBD_COL2/PIRQ3 KBD_COL3/PIRQ4 KBD_COL4/PIRQ5 KBD_COL5/PIRQ6 KBD_COL6/PIRQ7 KBD_COL7 KBD_ROW0 [CASL2] KBD_ROW1 [CASL3] KBD_ROW2 [CASH2] KBD_ROW3 [CASH3] KBD_ROW4 [RAS2] KBD_ROW5 [RAS3] KBD_ROW6 [MA12] KBD_ROW7 [PDACK1] KBD_ROW8 [PDRQ1] KBD_ROW9 [PIRQ2] Pin No. V14 G18 V3 T3 U4 U3 U2 W2 V4 Y2 W3 W1 V2 Y2 V18 W19 U20 R19 Y6 Y4 E2 D1 A2 B3 C3 A1 B2 C5 B19 D16 C17 B18 D15 C16 B17 D3 C2 E3 Signal Name KBD_ROW10 [BALE] KBD_ROW11 [SBHE] KBD_ROW12 [MCS16] KBD_ROW13 [[R32BFOE]] KBD_ROW14 / SUS_RES [LBL2] GPIO19 LF_HS LF_INT LF_LS MA0 {CFG0} MA1 {CFG1} MA2 MA3 {CFG3} MA4 MA5 MA6 MA7 MA8 MA9 MA10 MA11 [MA12] KBD_ROW6 [MCS16] KBD_ROW12 MEMR MEMW MWE [PDACK0] GPIO_CS11 [PDACK1] KBD_ROW7 [PDRQ0] GPIO_CS12 [PDRQ1] KBD_ROW8 [PE] GPIO26 [PIRQ0] GPIO_CS8 [PIRQ1] GPIO_CS7 [PIRQ2] KBD_ROW9 PIRQ3/KBD_COL2 PIRQ4/KBD_COL3 PIRQ5/KBD_COL4 PIRQ6/KBD_COL5 Pin No. D2 C1 F3 A3 Y12 V14 V5 Y3 W4 C10 B11 A12 B12 C11 A14 B13 C12 A15 B14 C13 A16 B17 F3 W20 T18 A11 W17 D3 Y17 C2 W2 W18 Y19 E3 A2 B3 C3 A1 ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet 37 PIN DESIGNATIONS (Pin Name)--ElanSC410 MICROCONTROLLER (Continued) Signal Name PIRQ7/KBD_COL6 [PPDWE] GPIO21 [PPOEN] GPIO22 [[R32BFOE]] KBD_ROW13 RAS0 RAS1 [RAS2] KBD_ROW4 [RAS3] KBD_ROW5 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved RESET RIN ROMCS0 ROMCS1 ROMRD ROMWR RSTDRV RTS SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 Pin No. B2 V3 T3 A3 C15 D14 D15 C16 M3 N2 P1 P3 R2 R3 T2 U1 V1 W5 Y7 V11 R18 T19 V20 U19 V12 W8 T20 P19 R20 N18 P20 N19 N20 M18 M20 L19 L18 L20 Signal Name SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 [SBHE] KBD_ROW11 SD0 [D16] SD1 [D17] SD2 [D18] SD3 [D19] SD4 [D20] SD5 [D21] SD6 [D22] SD7 [D23] SD8 [D24] SD9 [D25] SD10 [D26] SD11 [D27] SD12 [D28] SD13 [D29] SD14 [D30] SD15 [D31] SIN SIRIN SIROUT [SLCT] GPIO23 [SLCTIN] GPIO29 SOUT SPKR Pin No. K20 K19 J20 K18 K17 J19 H20 J18 H19 G20 G19 H18 F20 H17 C1 G3 F2 H3 G2 F1 H2 G1 J2 K3 K2 J1 K1 L1 L2 N1 L3 W11 Y9 V8 U4 W3 Y10 V7 Signal Name [STRB] GPIO31 SUS_RES/KBD_ROW14 [TC] GPIO_CS9 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC_A VCC_CPU VCC_CPU VCC_CPU VCC_CPU VCC_CPU VCC_CPU VCC_CPU VCC_RTC VL_ADS Pin No. V2 Y12 Y18 A8 A13 A18 B1 B4 B16 E1 E17 G17 H1 J3 J17 L17 M1 M17 M19 N17 P17 P18 T1 U18 V13 W9 Y1 Y16 W6 K4 L4 M4 N4 P4 R4 T4 W7 C19 38 ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet PIN DESIGNATIONS (Pin Name)--ElanSC410 MICROCONTROLLER (Continued) Signal Name VL_BE0 VL_BE1 VL_BE2 VL_BE3 VL_BLAST Pin No. F19 E20 F18 D20 A19 Signal Name VL_BRDY VL_D/C VL_LCLK VL_LDEV VL_LRDY Pin No. A20 E18 E19 F17 D19 Signal Name VL_M/IO VL_RST VL_W/R [XT_CLK] KBD_COL1 [XT_DATA] KBD_COL0 Pin No. C20 B20 D18 D1 E2 ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet 39 PIN STATE TABLES The pin state tables beginning on page 42 are grouped alphabetically by function and show pin states during reset, normal operation, and Suspend mode, along with output drive strength, maximum load, supply source, and power-down groups. s Normal Operation: The Normal Operation column covers the following power management modes: - Hyper-Speed mode - High-Speed mode - Low-Speed mode - Temporary Low-Speed mode - Standby mode s Suspend State: The letters used in the Suspend State column are defined in Table 3. Note that in Critical Suspend mode, pin terminations remain unchanged from the prior mode. Table 3. Pin Type Abbreviations Symbol [] {} Act B Meaning Brackets signify alternate state Reset configuration pin Not an output during Suspend mode Pin continues to function during Suspend mode Bidirectional Driven High (a logical 1) Pin is an input Input or open drain output Driven Low (a logical 0) Last state of the pin prior to entering Suspend mode Not applicable Pin is an active output Open drain output Pin is typically an open drain output, but can be configured as a Schmitt trigger input Built-in pulldown resistor Programmable pulldown or no resistor Programmable pullup or no resistor Programmable pullup or pulldown resistor Built-in pullup resistor 5-V safe pin Pin is a Schmitt trigger input Pin is typically a Schmitt trigger input, but can be configured as an open-drain output Three-state output Pin Characteristics The following information describes the individual column headings in the Pin State tables beginning on page 42. Most abbreviations are defined in Table 3. Drive types and power-down groups are defined in Tables 2 and 5, respectively. s Pin Number: The Pin Number column in all tables identifies the pin number of the individual I/O signal on the package. s Type: The abbreviations in the Type column for all tables are defined in Table 2. s Output Drive: The Output Drive column designates the output drive strength of the pin. The footnote after the drive strength letter designates that the drive strength is programmable. The available drive strengths are indicated in Table 2. Table 2. Output Drive A B C E 2 Drive Output Description IohTTL/IolTTL1 -3mA/3mA -6mA/6mA -12mA/12mA -18mA/18mA -24mA/24mA Vcc 3.0 V 3.0 V 3.0 V 3.0 V 3.0 V H I IOD L LS NA O OD OD-STI PD PPD PPU D 2 Notes: 1. The current out of a pin is given as a negative value. 2. Output drive is programmable. s Max Load: The Max Load column designates the load at which the I/O timing for that pin is guaranteed. It is also used to determine derated AC timing. s Supply: The Supply column identifies the VCC pin that supplies power for the specified I/O pin.The pin state table shows the pin state and termination for each power management unit mode. PPUD PU S STI STI-OD TS 40 ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet Table 4. Power Pin Type Abbreviations Symbol A CPU RTC VCC Meaning Pin is an analog input CPU power input Real-time clock input Power input s 5 V: An S in the 5 V column denotes pins that are 5-volt safe. This means these signals can tolerate 5 volts and they will not be damaged. However, they cannot drive to 5 volts. Using the Pin State Tables In the following Pin State tables, multiplexed pins include values specific to each signal in the row (across the table) where that signal is named. If a cell has only one value listed for two or three different signals, then this value is constant (does not change) no matter what signal is programmed to come out on the pin. s For example, in the table on page 47, when pin V14 is GPIO19, it is bidirectional; when pin V14 is LBL2, it is an output only. Because the cell includes two separate lines, the pin type is unique for each signal. s When the V14 pin is either GPIO19 or LBL2, the reset state is I-PU. Because there is only one value shown in the table, this value applies to both signals. s Power-Down Group: The signals on the chip are grouped together by interface for the purpose of powering down chips on the system board that are connected to these signals in Suspend mode. The letters A-I in the Power-Down Group column indicate the group with which each affected signal is associated. Only those signals that have a different Suspend state based on the interface powering off have a letter. The interfaces are identified in Table 5. The extended registers have bits that allow components connected to each interface to be powered down in Suspend mode. Care must be taken when designing a system with sections that power down, because many signals are shared between components. Table 5. Group A B C D E F G H I Interface DRAM ROM ISA (shared ISA signals individually enabled) Serial port, serial IrDA infrared port GPIO Chip Selects 1-0 VL bus PC Card Socket A PC Card Socket B and parallel port SD buffer control signals Power-Down Groups ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet 41 Table 6. Signal Name [Alternate Function] IOR IOW MEMR MEMW RSTDRV SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SD0 [D16] SD1 [D17] SD2 [D18] SD3 [D19] SD4 [D20] SD5 [D21] SD6 [D22] SD7 [D23] SD8 [D24] SD9 [D25] SD10 [D26] Pin # U20 R19 W20 T18 V12 T20 P19 R20 N18 P20 N19 N20 M18 M20 L19 L18 L20 K20 K19 J20 K18 K17 J19 H20 J18 H19 G20 G19 H18 F20 H17 G3 F2 H3 G2 F1 H2 G1 J2 K3 K2 J1 Type O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B [B] B [B] B [B] B [B] B [B] B [B] B [B] B [B] B [B] B [B] B [B] Pin State Table--System Interface1 Reset State H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD Normal Operation O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B-PPUD B-PPUD B-PPUD B-PPUD B-PPUD B-PPUD B-PPUD B-PPUD B-PPUD B-PPUD B-PPUD Suspend State H[TS-PD][TS] H[TS-PD][TS] H[TS-PD][TS] H[TS-PD][TS] TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD I-PD I-PD I-PD I-PD I-PD I-PD I-PD I-PD I-PD I-PD I-PD Power Down Group C C C C Note 2 2 2 2 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 5 5 5 5 5 5 5 5 5 5 5 Max Output Load Supply Drive (pF) C C C C A C-E4 C-E4 C-E4 C-E4 C-E4 C-E4 C-E C-E C-E 4 4 4 5V S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S 50 50 50 50 30 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 50 50 4 4 4 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC C-E4 C-E 4 4 4 C-E C-E C-E C-E4 4 4 4 C-E C-E C-E C-E C-E C-E B B C-E C-E C-E4 4 4 4 C-E4 4 4 C-E 70 70 70 70 70 70 70 70 70 70 70 C-E C-E C-E C-E4 4 4 4 C-E C-E4 C-E C-E 4 4 4 C-E 42 ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet Table 6. Signal Name [Alternate Function] SD11 [D27] SD12 [D28] SD13 [D29] SD14 [D30] SD15 [D31] Pin # K1 L1 L2 N1 L3 Type B [B] B [B] B [B] B [B] B [B] Pin State Table--System Interface1 (Continued) Reset State TS-PD TS-PD TS-PD TS-PD TS-PD Normal Operation B-PPUD B-PPUD B-PPUD B-PPUD B-PPUD Suspend State I-PD I-PD I-PD I-PD I-PD Power Down Group Note 5 5 5 5 5 Max Output Load Supply Drive (pF) C-E4 C-E C-E 4 5V S S S S S 70 70 70 70 70 VCC VCC VCC VCC VCC C-E4 4 C-E4 Notes: 1. Pin states for AEN, IOCHRDY, IOCS16, PDACK0, PDRQ0, TC, and PIRQ1-PIRQ0 are listed in Table 9 on page 49. Pin states for BALE, MCS16, SBHE, PDACK1, PDRQ1 and PIRQ7-PIRQ2 are listed in Table 14 on page 53. 2. The ISA control signals have three programmable options for Suspend mode: -Driven High (inactive). -Three-stated with no pullup or pulldown. This is useful when the ISA device is at 5 V and left powered in Suspend. The board design should not drive 3.3-V signals into a 5-V device during Suspend because this can waste power. The system designer should provide large pullup resistors to 5 V for each of these signals on the board if this configuration is programmed. - Three-stated with pulldown resistors when suspended with the intent of powering off the ISA device (Power-Down Group C). Be careful when handling IOR and IOW because they are shared with the PC Card sockets and may need to be buffered if certain combinations of system components are powered up and off. Summary: These pins have built-in pulldown resistors that are invoked by: -Suspend mode and the ISA interface is programmed to be powered off in Suspend mode (Power-Down Group C). 3. The SA bus, SA25-SA0, and the RSTDRV signal are three-stated with pulldowns in Suspend mode. This accommodates having the ISA bus, PC Card sockets, VL bus, and ROM interfaces left powered on or powered off in Suspend mode. Summary: These pins have built-in pulldown resistors that are invoked by: -Suspend mode. 4. C, D, and E output drives are programmable. 5. The combination of SD15-SD0 and D31-D16 on the same pins requires the signals to be pulled up in SD bus mode (for PC compatibility) and pulled down in D bus mode (for consistency with D15-D0). Regardless of the mode the bus is in, the pins are in the input state (i.e., they are still bidirectional and are not driven as outputs) and pulled down in Suspend mode. These signals are pulled up or down automatically depending on whether the SD buffer is enabled or not (CFG3), and whether the system is in Suspend mode or not. Summary: These pins have built-in pulldown and pullup resistors that are invoked by: -Reset invokes the pulldown resistors. -Suspend mode invokes the pulldown resistors. -Operating (Hyper/High/Low/Temp Low-Speed modes): the pins will have pullups if the SD buffer control signals are enabled, and have pulldowns otherwise. ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet 43 Table 7. Signal Name [Alternate Function] CASH0 CASH1 CASL0 CASL1 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 KBD_ROW0 [CASL2] KBD_ROW1 [CASL3] KBD_ROW2 [CASH2] KBD_ROW3 [CASH3] KBD_ROW4 [RAS2] KBD_ROW5 [RAS3] KBD_ROW6 [MA12] MA0 {CFG0} MA1 {CFG1} MA2 {CFG2} MA3 {CFG3} MA4 MA5 MA6 MA7 MA8 MA9 Pin # D13 A17 B15 C14 B10 A10 C9 B9 A9 B8 C8 A7 B7 A6 C7 B6 A5 C6 B5 A4 B19 D16 C17 B18 D15 C16 B17 C10 B11 A12 B12 C11 A14 B13 C12 A15 B14 Type O O O O B B B B B B B B B B B B B B B B STI-OD [O] STI-OD [O] STI-OD [O] STI-OD [O] STI-OD [O] STI-OD [O] STI-OD [O] O {I} O {I} O {I} O {I} O O O O O O Pin State Table--Memory Interface1 Reset State H H H H TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD I-PU I-PU I-PU I-PU I-PU I-PU I-PU I-PD I-PD I-PD I-PD I-PD L L L L L Normal Operation O O O O B-PD B-PD B-PD B-PD B-PD B-PD B-PD B-PD B-PD B-PD B-PD B-PD B-PD B-PD B-PD B-PD IOD-PU O IOD-PU O IOD-PU O IOD-PU O IOD-PU O IOD-PU O IOD-PU O O O O O O O O O O O Suspend State O[L][TS-PD] O[L][TS-PD] O[L][TS-PD] O[L][TS-PD] TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD I-PU O[L][TS-PD] I-PU O[L][TS-PD] I-PU O[L][TS-PD] I-PU O[L][TS-PD] I-PU O[L][TS-PD] I-PU O[L][TS-PD] I-PU TS-PD TS-PPD TS-PPD TS-PPD TS-PPD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD A 2 Max Output Load Supply Drive (pF) D D D D C-E 3 Power Down Group A A A A Note 5 V 2 2 2 2 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 2 30 30 30 30 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 250 250 250 250 250 250 250 70 70 70 70 70 70 70 70 70 70 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC C-E3 C-E3 C-E3 C-E 3 C-E3 C-E3 C-E3 C-E3 C-E3 C-E3 C-E3 C-E3 C-E3 C-E3 C-E3 D D D D C-E3 C-E3 C-E3 C-E3 C-E3 C-E3 C-E3 C-E3 C-E3 C-E3 C-E3 C-E3 C-E3 A 2 A 2 A 2 A 2 A 5 6 6 6, 7 6 6, 8 8 8 8 8 8 44 ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet Table 7. Signal Name [Alternate Function] MA10 MA11 MWE RAS0 RAS1 ROMCS0 ROMCS1 ROMRD ROMWR Pin # C13 A16 A11 C15 D14 R18 T19 V20 U19 Type O O O O O O O O O Pin State Table--Memory Interface 1 (Continued) Reset State L L H H H H H H H Normal Operation O O O O O O O O O Suspend State TS-PD TS-PD H[TS-PD] O[L][TS-PD] O[L][TS-PD] H[TS-PD][TS] H[TS-PD][TS] H[TS-PD][TS] H[TS-PD][TS] A A A B B B B Power Down Group Note 5 V 8 8 2 2 2 9 9 9 9 Max Output Load Supply Drive (pF) C-E3 C-E3 C-E3 C-E3 C-E B B B B 3 70 70 70 50 50 50 50 50 50 VCC VCC VCC VCC VCC VCC VCC VCC VCC S S S S Notes: 1. Pin states for D31-D16 are listed in Table 6 on page 42. 2. RAS3-RAS0, CASH3-CASH0, CASL3-CASL0, and MWE Suspend state of the pins: -The RAS and CAS signals remain active if the DRAM interface is configured for CAS-before-RAS refresh in Suspend mode. -The RAS and CAS signals will be Low if the DRAM is configured for self-refresh in Suspend mode. -Will be three-stated with a pulldown resistor if the DRAM interface is programmed to be disabled so the DRAM can be powered down (Power-Down Group A). -Will not be affected by this when the RAS and CAS signals that share pins with other functions (RAS3-RAS2, CASH3- CASH2, and CASL3-CASL2) are not enabled to come out of the chip. -The MWE signal will be driven out High (deasserted) when the DRAM is programmed to be left powered (Power-Down Group A). Summary: These pins have built-in pulldown resistors that are invoked by: -Suspend mode and DRAM interface programmed for power-down in Suspend (Power-Down Group A), and the pins are enabled as RAS/CAS for RAS3-RAS2, CASH3-CASH2, and CASL3-CASL2. 3. C, D, and E output drives are programmable. 4. The data bus D15-D0 has built-in pulldown resistors that are invoked when the data bus signals are inputs. 5. Memory Address MA12 Suspend state of the pin: Will be three-stated with a pulldown resistor. This will work for CAS-before-RAS refresh, self-refresh, and the DRAM powered down. Summary: This pin has a built-in pulldown resistor that is invoked by Suspend mode. 6. Memory Address MA4-MA0 pins are shared with the power-on configuration signals so the reset state of the pins has a pulldown resistor on these signals. This default configuration will choose: not test mode and an 8-bit ROM/Flash memory accessed by ROMCS0 with the SD buffer-control signals disabled. The pulldown resistors are from 50 K to 150 K; they need to be overridden by pullup resistors on the board if other configurations are needed. These pulldown resistors are disabled after reset; they are not active during normal chip operation. For configuration signals CFG0, CFG1, CFG2, and CFG3, if the system uses the default configuration, the pulldown resistors will be active again in Suspend mode. If external pullup resistors are used on the board for a different configuration, the pins with external pullups will three-state in Suspend mode without pulldown resistors. The reserved signal on MA4 is only used for AMD testing; it should not be pulled up on the system design. This pin will always go to three-state with a pulldown resistor in Suspend mode. Summary: Each pin has a built-in pulldown resistor that is invoked by: -Reset -Suspend mode and the configuration pin being Low during reset (for CFG3-CFG0). -Suspend mode for the reserved signal on MA4. ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet 45 7. The CFG2 pin is not supported on the ElanSC410 microcontroller. 8. Memory Address MA11-MA4 Suspend state of the pins: Will be three-stated with a pulldown resistor. This will work for CAS-before-RAS refresh, self-refresh, and the DRAM powered down. Summary: These pins have built-in pulldown resistors that are invoked by Suspend mode. 9. The ROM control signals have three programmable options for Suspend mode: -Driven High (inactive) -Three-stated with no pullup or pulldown. This is useful when the ROM is at 5 V and left powered in Suspend. The board design should not drive 3.3-V signals into a 5-V device during Suspend, because this can waste power. The system designer could provide large pullup resistors to 5 V for each of these signals on the board if this configuration is programmed. - Three-stated with pulldown resistors when suspended with the intent of powering off the ROMs (Power-Down Group B). Summary: These pins have built-in pulldown resistors that are invoked by: -Suspend mode; and the ROM interface is programmed to be powered off in Suspend mode (Power-Down Group B). 46 ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet Table 8. Signal Name [Alternate Function] GPIO15 [PCMA_VPP2] GPIO16 [PCMB_VCC] Pin # Y15 V15 Type B [O] B [O] B [O] B [O] B [O] B [I] B [O] Pin State Table--GPIOs/Parallel Port/PC Card Socket B Max Output Load Supply Drive (pF) B B B B B B C 50 50 50 50 50 50 30 VCC VCC VCC VCC VCC VCC VCC Reset State I-PD I-PD I-PD I-PD I-PU I-PU I-PU Normal Operation I-PPD[O] O I-PPD[O] O I-PPD[O] O I-PPD[O] O I-PPU[O] O I-PPU[O] I-PPU I-PPU[O] O TS-PD I-PPU[O] O TS-PD I-PPU[O] I-PU I-PPU I-PPU[O] I-PU I-PPU I-PPU[O] I-PU I-PPU I-PPU[O] I-PU I-PPU I-PPU[O] I-PU I-PPU I-PPU[O] OD-PU[O] O I-PPU[O] OD-PU[O] O I-PPU[O] OD-PU[O] O I-PPU[O] OD-PU[O] O I-PPD[O] O I-PPD[O] O Suspend State I-PPD[O] O I-PPD[O] O I-PPD[O] O I-PPD[O] O I-PPU[O] O I-PPU[O] I-PPUD I-PPU[O] H[TS-PD][TS] TS-PD I-PPU[O] H[TS-PD][TS] TS-PD I-PPU[O] I-PU[I-PD] I-PPUD I-PPU[O] I-PU[I-PD] I-PPUD I-PPU[O] I-PU[I-PD] I-PPUD I-PPU[O] I-PU[I-PD] I-PPUD I-PPU[O] I-PU[I-PD] I-PPUD I-PPU[O] OD-PU[OD-PD] H[TS-PD][TS] I-PPU[O] OD-PU[OD-PD] L[TS-PD] I-PPU[O] OD-PU[OD-PD] H[TS-PD][TS] I-PPU[O] OD-PU[OD-PD] H[TS-PD][TS] I-PPD[O] O I-PPD[O] O G H Power Down Group Note 1,2 5V 1, 2 GPIO17 W15 [PCMB_VPP1] GPIO18 [PCMB_VPP2] GPIO19 [LBL2] GPIO20 [CD_A2] GPIO21 [PPDWE] (PC Card Enabled) GPIO22 [PPOEN] (PC Card Enabled) GPIO23 [SLCT] [WP_B] GPIO24 [BUSY] [BVD2_B] GPIO25 [ACK] [BVD1_B] GPIO26 [PE] [RDY_B] GPIO27 [ERROR] [CD_B] GPIO28 [INIT] [REG_B] GPIO29 [SLCTIN] [RST_B] GPIO30 [AFDT] [MCEH_B] GPIO31 [STRB] [MCEL_B] GPIO_CS13 [PCMA_VCC] Y14 V14 G18 V3 1, 2 1, 2 1 1, 2 S S 3 T3 B [O] C 30 VCC I-PU H 3 S U4 B [I] [I] B [I] [I] B [I] [I] B [I] [I] B [I] [I] B [OD][O] [O] B [OD][O] [O] B [OD][O] [O] B [OD][O] [O] B [O] B [O] D 150 VCC I-PU H 2, 3 S U3 D 150 VCC I-PU H 2, 3 S U2 D 150 VCC I-PU H 2, 3 S W2 D 150 VCC I-PU H 2, 3 S V4 D 150 VCC I-PU H 2, 3 S Y2 D 150 VCC OD-PU H 2, 3 S W3 D 150 VCC OD-PU H 2, 3 S W1 D 150 VCC OD-PU H 2, 3 S V2 D 150 VCC OD-PU H 2, 3 S V16 B B 50 50 VCC VCC I-PD I-PD 1, 2 GPIO_CS14 W16 [PCMA_VPP1] 1, 2 ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet 47 Notes: 1. The shared GPIO20-GPIO15, GPIO_CS14-GPIO_CS13, and PC Card battery signals: As GPIO_CSxs, the signals are active in Suspend mode: that is, if they are inputs before Suspend, they are still inputs during Suspend (the GPIO_CSs can be used to wake up the system); if they are outputs before Suspend, they are still outputs during Suspend (the GPIO_CSs can be programmed to change state by mode). As inputs, the pullup or pulldown on the signal can be disabled; if disabled, it is disabled in all modes. When the signal is an output, the built-in resistors are automatically disabled. When enabled, the Latched Battery Low Detect function (LBL2) that is shared on GPIO19 is an output in all modes; there are no pullup or pulldown resistors active. On the ElanSC400 microcontroller, the PC Card functions shared on these pins are programmable by PC Card socket; the pin multiplexing options are explained earlier in this document. For the PC Card power control (PCMA_VCC, PCMA_VPP1, PCMA_VPP2, PCMB_VCC, PCMB_VPP1, PCMB_VPP2), the signals are outputs for each mode. For the second Card Detect (CD_A2): -Reset invokes pullup. -During normal operation, the pullup resistor can be disabled by a register bit. -During Suspend mode, the input will have a pulldown if the PC Card Socket A interface is programmed to be powered off in Suspend mode (Power-Down Group G). If the socket is not programmed to be powered off in Suspend mode, the input will have the same state as when operating: the pullup is programmable to be enabled or not. 2. The PC Card signals MCEL_B, MCEH_B, RST_B, REG_B, CD_B, RDY_B, BVD1_B, BVD2_B, WP_B, CD_A2, PCMB_VPP2, PCMB_VPP1, PCMB_VCC, PCMA_VPP1, PCMA_VPP2, and PCMA_VCC are not supported on the ElanSC410 microcontroller. 3. The shared parallel port, PC Card Socket B control, and GPIO signals: -These signals default to the GPIO interface on reset. -As a parallel port in Suspend mode, these signals are programmable to accommodate the parallel port powered up or down. -As PC Card control on the ElanSC400 microcontroller, these signals have the same features as the Socket A control signals. -As GPIOs, these signals are not handled specially in Suspend, they remain the same as they were when the chip was active (i.e., they remain as inputs with the pullup enabled or not, or continue to drive out the same value if they were outputs). Summary: Shared parallel port/PC Card Socket B/GPIO signals: Built-in pullup and pulldown resistors that are invoked by: -Reset invokes pullups -As parallel port signals: *Operating: pullups are enabled if not EPP mode. Outputs without pullup or pulldowns if EPP mode. *Suspend: pullups are enabled, unless the parallel port is programmed to be powered off in Suspend mode, in which case pulldowns are enabled. *If EPP mode is enabled for the parallel port, the outputs are driven out at their last value in Suspend mode. -As PC Card Socket B signals (ElanSC400 microcontroller only): *Operating: outputs have no pullups or pulldowns; inputs have pullups that can be disabled by programming a bit. *Suspend: outputs are driven out inactive with no pullups or pulldowns unless the PC Card Socket B is programmed to be powered off in Suspend mode; then the outputs go to three-state with pulldown resistors; inputs will be the same as they were when operating, with a pullup resistor that can be disabled by programming, unless the PC Card Socket B is programmed to be powered off in Suspend mode (Power-Down Group H), in which case the inputs have pulldown resistors enabled. -As GPIO signals: *Operating or Suspend: as outputs they have no pullups or pulldowns; as inputs they have pullups that can be disabled by programming a bit; no change of state when the system goes to Suspend. 48 ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet Table 9. Signal Name [Alternate Function] GPIO_CS5 [IOCS16] GPIO_CS6 [IOCHRDY] GPIO_CS7 [PIRQ1] GPIO_CS8 [PIRQ0] GPIO_CS9 [TC] GPIO_CS10 [AEN] GPIO_CS11 [PDACK0] GPIO_CS12 [PDRQ0] Pin # W19 V18 Y19 W18 Y18 V17 W17 Y17 Type B [I] B [STI] B [I] B [I] B [O] B [O] B [O] B [I] Pin State Table--GPIOs/ISA Bus Reset State I-PU I-PU I-PU I-PU I-PU I-PU I-PU I-PD Normal Operation I-PPU[O] I-PU I-PPU[O] I-PU I-PPU[O] I-PU I-PPU[O] I-PU I-PPU[O] O I-PPU[O] O I-PPU[O] O I-PPD[O] I-PD Suspend State I-PPU[O] I-PU[I-PD] I-PPU[O] I-PU[I-PD] I-PPU[O] I-PU[I-PD] I-PPU[O] I-PU[I-PD] I-PPU[O] TS-PD I-PPU[O] TS-PD I-PPU[O] H[TS-PD][TS] I-PPD[O] I-PD C 1 Max Output Load Supply Drive (pF) B B B B C C C B 50 50 50 50 50 50 50 50 VCC VCC VCC VCC VCC VCC VCC VCC Power Down Group C Note 1 5V S S S S S S S S 1 C 1 C 1 C 1 1 1 ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet 49 Notes: 1. The shared GPIO_CS12-GPIO_CS5 and ISA signals: As GPIO_CS signals, they are active in Suspend mode: that is, if they are inputs before Suspend, they are still inputs during Suspend (they can be used to wake up the system); if they are outputs before Suspend, they are still outputs during Suspend (they can be programmed to change state by mode). As inputs, the pullup or pulldown on the signal can be disabled; if disabled, it is disabled in all modes. When the signal is an output, the built-in resistors are automatically disabled. The ISA function for each pin is programmable by functional group: that is, the system can choose to use PIRQ0 and still use the DMA pins as GPIO_CSxs (the pin multiplexing options are explained elsewhere in this document). As ISA signals, these pins are programmable to support a system with ISA peripherals powered up or down in Suspend mode (Power-Down Group C). For those signals that are High when deasserted, there is an option to three-state them with no built-in resistors, so an external resistor can be placed on the board to pull them up to 5 V. Summary: GPIO_CS12: Built-in pulldown resistor that is invoked by: -Reset -ISA signal enabled on this pin (the pin will be PDRQ0). -The pulldown is disabled by this pin being a GPIO_CS and an output. -The pulldown can be programmed to be disabled when the pin is a GPIO_CS input. Summary: GPIO_CS11: Built-in pullup and pulldown resistors that are invoked by: -Reset invokes the pullup. -When enabled as the ISA signal PDACK0: *In normal operation, this signal is an output and no pullup or pulldown is needed. *The pulldown is invoked by Suspend mode and the ISA bus is programmed to be powered off in Suspend (PowerDown Group C). *If the ISA bus is programmed for 5-V use and is not powered down in Suspend, then this signal is three-state without a built-in pullup or pulldown resistor. -When enabled as the GPIO_CS11 signal: *As an output, the pullup and pulldown are disabled in all modes, and these GPIO_CSx signals can be active in Suspend. *As an input, the pullup can be programmed to be enabled or disabled; this will then be the state of the pin in all modes, including Suspend. Summary: GPIO_CS10-GPIO_CS9: Built-in pullup and pulldown resistors that are invoked by: -Reset invokes the pullups. -When enabled as the ISA signals AEN and TC: *In normal operation, these signals are outputs and no pullup or pulldown is needed. *The pulldowns are invoked by Suspend mode. -When enabled as the GPIO_CS10-GPIO_CS9 signals: *As an output, the pullup and pulldown are disabled in all modes, and these GPIO_CS signals can be active in Suspend. *As an input, the pullup can be programmed to be enabled or disabled; this will then be the state of the pin in all modes, including Suspend. Summary: GPIO_CS8-GPIO_CS5: Built-in pullup and pulldown resistors that are invoked by: -Reset invokes the pullups. -When enabled as PIRQ1-PIRQ0, IOCHRDY, and IOCS16: *In normal operation and Suspend, these signals are inputs and the pullup resistors are active. *The pulldowns are invoked by Suspend mode and the ISA bus interface programmed for power off in Suspend (Power-Down Group C). -When enabled as the GPIO_CS8-GPIO_CS5 signals: *As an output, the pullup and pulldown are disabled in all modes, and these GPIO_CSx signals can be active in Suspend. *As an input, the pullup can be programmed to be enabled or disabled; this will then be the state of the pin in all modes, including Suspend. 50 ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet Table 10. Pin State Table--GPIOs/System Data (SD) Buffer Control Signal Name [Alternate Function] GPIO_CS2 [[DBUFRDL]] GPIO_CS3 [[DBUFRDH]] GPIO_CS4 [[DBUFOE]] KBD_ROW13 [[R32BFOE]] Pin # C18 D17 C4 A3 Type B [[O]] B [[O]] B [[O]] STI-OD [O] Max Output Load Supply Drive (pF) C C C C 50 50 50 250 VCC VCC VCC VCC Reset State I-PU I-PU I-PU I-PU Normal Operation I-PPU[O] O I-PPU[O] O I-PPU[O] O IOD-PU O Suspend State I-PPU[O] TS-PD I-PPU[O] TS-PD I-PPU[O] H[TS-PD][TS] I-PU H[TS-PD][TS] I I Power Down Group Note 1 5V 1 1 S S 2 Notes: 1. The data buffer control signals are shared with the GPIO_CS4-GPIO_CS2 signals and with the keyboard row signal: When the data buffer control signals are enabled on the pins, they will drive inactive during Suspend mode, go three-state without resistors to allow an external resistor to 5 V, or three-state with a pulldown to support powering off the data buffer. Summary: GPIO_CS4-GPIO_CS2/DBUFOE/DBUFRDH/DBUFRDL: Built-in pullup and pulldown resistors that are invoked by: -Reset invokes pullup. -When buffer control is invoked by the configuration pin, these pins are outputs without any pullups or pulldowns. -When buffer control is enabled and in Suspend mode, DBUFRDH and DBUFRDL are three-state with the pulldowns enabled; DBUFOE has three options: *High (inactive) with no pullup or pulldown. *Three-state with a pulldown if it is programmed for the buffer to be powered off in Suspend mode (Power-Down Group I). *Three-state with no pulldown if it is programmed for the buffer to be powered on in Suspend mode and at 5 V. -When enabled as the GPIO_CS4-GPIO_CS2 signals: *As an output, the pullup and pulldown are disabled in all modes, and these GPIO_CS signals can be active in Suspend. *As an input, the pullup can be programmed to be enabled or disabled. This will then be the state of the pin in all modes, including Suspend. 2. This data buffer control signal (R32BFOE) is shared with the keyboard row signal: When the data buffer control signals are enabled on the pins, they will drive inactive during Suspend mode, go three-state without resistors to allow an external resistor to 5 V, or three-state with a pulldown to support powering off the data buffer. Summary: KBD_ROW13/R32BFOE: Built-in pullup and pulldown resistors that are invoked by: -Reset invokes the pullup. -As R32BFOE, this pin is an output without a pullup or pulldown. -When buffer control is enabled and in Suspend mode, R32BFOE has three options: *High (inactive) with no pullup or pulldown. *Three-state with a pulldown if it is programmed for the buffer to be powered off in Suspend mode. *Three-state with no pulldown if it is programmed for the buffer to be powered on in Suspend mode and at 5 V. -When enabled as the keyboard row signal, this signal has a pullup enabled at all times. ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet 51 Table 11. Signal Name [Alternate Function] GPIO_CS0 GPIO_CS1 Pin # V19 Y20 Type B B Pin State Table--GPIOs Reset State I-PU I-PU Normal Operation I-PPU[O] I-PPU[O] Suspend State I-PPU[O] I-PPU[O] Power Down Group E E Note 1 1 Max Output Load Supply Drive (pF) B 50 VCC B 50 VCC 5V S S Notes: 1. The GPIO_CS signals become inputs in Suspend mode with either a pullup resistor for devices that are left powered, or a pulldown resistor for devices that are to be powered off. Summary: GPIO_CS1-GPIO_CS0: Built-in pullup and pulldown resistors that are invoked by: Reset invokes pullup. When enabled as the GPIO_CS1-GPIO_CS0 signals: As an output, the pullup and pulldown are disabled in all modes, and these GPIO_CSxs can be active in Suspend. As an input, the pullup can be programmed to be enabled or disabled; this will then be the state of the pin in all modes, including Suspend. Table 12. Signal Name [Alternate Function] CTS DCD DSR DTR RIN RTS SIN SOUT Pin # V10 V9 W10 Y8 V11 W8 W11 Y10 Type I I I O I O I O Pin State Table--Serial Port Reset State I-PU I-PU I-PU H I-PU H I-PU H Normal Operation I-PU [I-PD] I-PU [I-PD] I-PU [I-PD] O [TS-PD] I-PU [I-PD] O [TS-PD] I-PU [I-PD] O [TS-PD] Suspend State I-PU[I-PD] I-PU[I-PD] I-PU[I-PD] TS-PD I-PU[I-PD] TS-PD I-PU[I-PD] TS-PD Power Down Group D D D D D Note 1 1 1 1 1 1 1 1 Max Output Load Supply Drive (pF) VCC VCC VCC A 30 VCC VCC A 30 VCC VCC A 30 VCC 5V Notes: 1. The serial port output signals are three-state with built-in pulldown resistors in Suspend mode. The serial port input signals can be left as inputs with pullups for a Suspend when the serial device is left powered. Or, they can be configured as inputs with pulldown resistors if the serial device is to be powered off (Power-Down Group D). Summary: The serial port output pins have built-in pulldown resistors that are invoked by Suspend mode. Summary: The serial port input pins have built-in pullup and pulldown resistors that are invoked by: -Reset invokes the pullup resistors. -Operating: the pullup resistors are enabled. -Suspend mode invokes the pulldown resistors if the serial interface is programmed to be powered off in Suspend (PowerDown Group C); otherwise there are pullup resistors in Suspend mode. Table 13. Signal Name [Alternate Function] SIRIN SIROUT Pin # Y9 V8 Type I O Pin State Table--Infrared Interface Reset State I-PD L Normal Operation I-PPD O Suspend State I-PPD TS-PD Power Down Group Note 1 1 Max Output Load Supply Drive (pF) VCC A 30 VCC 5V Notes: 1. The serial infrared interface output and input settle to Suspend states that allow the device to be powered up or off. The output is three-state with a built-in pulldown resistor, and the input has a built-in pulldown resistor. The pulldown resistor on the input pin (SIRIN) can be programmed to be disabled during normal operation and Suspend mode. Summary: The serial infrared input pin has a built-in pulldown resistor that is invoked by: -Reset invokes the pulldown resistor. -The pulldown resistor is then programmable to be there or not. 52 ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet Table 14. Signal Name [Alternate Function] KBD_COL0 [XT_DATA] KBD_COL1 [XT_CLK] KBD_COL2/ PIRQ3 KBD_COL3/ PIRQ4 KBD_COL4/ PIRQ5 KBD_COL5/ PIRQ6 KBD_COL6/ PIRQ7 KBD_COL7 KBD_ROW0 [CASL2] KBD_ROW1 [CASL3] KBD_ROW2 [CASH2] KBD_ROW3 [CASH3] KBD_ROW4 [RAS2] KBD_ROW5 [RAS3] KBD_ROW6 [MA12] KBD_ROW7 [PDACK1] KBD_ROW8 [PDRQ1] KBD_ROW9 [PIRQ2] KBD_ROW10 [BALE] KBD_ROW11 [SBHE] KBD_ROW12 [MCS16] KBD_ROW13 [[R32BFOE]] Pin # E2 D1 A2 B3 C3 A1 B2 C5 B19 D16 C17 B18 D15 C16 B17 D3 C2 E3 D2 C1 F3 A3 Type OD-STI [B] OD-STI [B] OD-STI [I] OD-STI [I] OD-STI [I] OD-STI [I] OD-STI [I] OD-STI STI-OD [O] STI-OD [O] STI-OD [O] STI-OD [O] STI-OD [O] STI-OD [O] STI-OD [O] STI-OD [O] STI-OD [I] STI-OD [I] STI-OD [O] STI-OD [O] STI-OD [I] STI-OD [O] Pin State Table--Keyboard Interface Reset State ODPU ODPU ODPU ODPU ODPU ODPU ODPU ODPU I-PU I-PU I-PU I-PU I-PU I-PU I-PU I-PU I-PU I-PU I-PU I-PU I-PU I-PU Normal Operation IOD-PPUD IOD-PPUD IOD-PPUD IOD-PPUD IOD-PPUD I-PPUD IOD-PPUD I-PPUD IOD-PPUD I-PPUD IOD-PPUD I-PPUD IOD-PPUD I-PPUD IOD-PPUD IOD-PU O IOD-PU O IOD-PU O IOD-PU O IOD-PU O IOD-PU O IOD-PU O IOD-PU O IOD-PU I-PD IOD-PU I-PU IOD-PU O IOD-PU O IOD-PU I-PU IOD-PU O Suspend State IOD-PPUD IOD-PPUD IOD-PPUD IOD-PPUD IOD-PPUD I-PPUD[I-PD] IOD-PPUD I-PPUD[I-PD] IOD-PPUD I-PPUD[I-PD] IOD-PPUD I-PPUD[I-PD] IOD-PPUD I-PPUD[I-PD] IOD-PPUD I-PU O[L][TS-PD] I-PU O[L][TS-PD] I-PU O[L][TS-PD] I-PU O[L][TS-PD] I-PU O[L][TS-PD] I-PU O[L][TS-PD] I-PU TS-PD I-PU H[TS-PD][TS] I-PU I-PD I-PU I-PU[I-PD] I-PU TS-PD I-PU H[TS-PD][TS] I-PU I-PU[I-PD] I-PU H[TS-PD][TS] C S C I 4 Max Output Load Supply Drive (pF) D D D D D D D D D D D D P-C,E P-C,E P-C,E C C C C C C C 250 250 250 250 250 250 250 250 250 250 250 250 250 250 250 250 250 250 250 250 250 250 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Power Down Group Note 1 5V S S S S S S S 1 1 C 1 C 1 C 1 C 1 C 1 2 A 2 A 2 A 2 A 2 A 2 A 3 S C S S C S S S ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet 53 Notes: 1. The keyboard column signals are shared with the programmable IRQs and XT keyboard signals. As keyboard column signals and XT keyboard signals, they are inputs and open drain outputs with pullup or pulldown resistors in normal operation and Suspend mode. Each column signal is individually programmable for the pullup or pulldown in the keyboard extended registers. As IRQs, the pins are inputs with built-in pullup or pulldown resistors (use the same registers in the keyboard controller to enable pullups or pulldowns). During Suspend mode, they stay as inputs with the pullup or pulldown. Or, if Power-Down Group C is enabled for the ISA bus to be powered down in Suspend mode and a bit is set identifying that these signals are being used as IRQs, they will have pulldown resistors activated. There is no programmable bit to make these signals IRQs beyond the extended register in the interrupt controller that maps the pin to a particular IRQ. If the system must use any of these as IRQs, a bit must be set, notifying the chip, so that they can have the pulldown resistors invoked in Suspend mode. Summary: As keyboard column and XT keyboard signals: -Pullup or pulldown resistor depending on the setting of the Keyboard Column Pullup/Pulldown register in the keyboard controller. Summary: As programmable IRQ signals: -Pullup or pulldown resistors during normal operation and Suspend (depending on the configuration register in the keyboard controller. -Pulldown resistors during suspend if Power-Down Group C (the ISA bus) is enabled for power-down in Suspend, and a bit is set indicating that these signals are used as IRQs and need to be pulled down in Suspend. 2. RAS3-RAS2, CASH3-CASH2, and CASL3-CASL2 Suspend state of the pins: -The RAS and CAS signals remain active if the DRAM interface is configured for CAS-before-RAS refresh in Suspend mode. -The RAS and CAS signals will be Low if the DRAM is configured for self-refresh in Suspend mode. -Will be three-stated with a pulldown resistor if the DRAM interface is programmed to be disabled so the DRAM can be powered down (Power-Down Group A). -Will not be affected by this when the RAS and CAS signals that share pins with other functions are not enabled to come out of the chip. Summary: These pins have built-in pulldown resistors that are invoked by: -Suspend mode and DRAM interface programmed for power-down in Suspend (Power-Down Group A), and the pins are enabled as RAS/CAS for RAS3-RAS2, CASH3-CASH2, and CASL3-CASL2. 3. Memory Address MA12 Suspend state of the pin: Will be three-stated with a pulldown resistor. This will work for CAS-before-RAS refresh, self-refresh, and the DRAM powered down. Summary: This pin has a built-in pulldown resistor that is invoked by Suspend mode. 4. The data buffer control signal R32BFOE that is shared with the keyboard row signal: When the data buffer control signals are enabled on the pins, they will drive inactive during Suspend mode, go three-state without resistors to allow an external resistor to 5 V, or three-state with a pulldown to support powering off the data buffer. Summary: KBD_ROW13/R32BFOE: Built-in pullup and pulldown resistors that are invoked by: -Reset invokes the pullup. -As R32BFOE, this pin is an output without a pullup or pulldown. -When buffer control is enabled and in Suspend mode, R32BFOE has three options: *High (inactive) with no pullup or pulldown. *Three-state with a pulldown if it is programmed for the buffer to be powered off in Suspend mode. *Three-state with no pulldown if it is programmed for the buffer to be powered on in Suspend mode and at 5 V. -When enabled as the keyboard row signal, this signal has a pullup enabled at all times. 54 ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet Table 15. Signal Name [Alternate Function] BVD1_A BVD2_A CD_A ICDIR MCEH_A [[BNDSCN_TMS]] MCEL_A [[BDNSCN_TCK]] OE RDY_A REG_A [[BNDSCN_TDO]] RST_A [[BNDSCN_TDI]] WAIT_AB WE WP_A Pin # V1 R3 R2 M3 N3 P2 P1 P3 M2 R1 U1 N2 T2 Type I I I O O [[I]] O [[I]] O I O [[O]] O [[I]] I O I B B B B B B B Pin State Table--PC Card Socket A Reset State I-PU I-PU I-PU L H H H I-PU H O I-PU H I-PU Normal Operation I-PPU I-PPU I-PPU O O [I-PD] O [I-PD] O I-PPU O [O] O [I-PD] I-PPU O I-PPU Suspend State I-PPUD I-PPUD I-PPUD H[TS-PD][TS] H[TS-PD][TS] H[TS-PD][TS] H[TS-PD][TS] I-PPUD H[TS-PD][TS] L[TS-PD] I-PPUD H[TS-PD][TS] I-PPUD Power Down Group G G G G G G G G G G G G G Note 5 V 1,2 1, 2 1, 2 1, 2 1, 2 Max Output Load Supply Drive (pF) VCC VCC VCC 50 50 50 50 50 50 VCC VCC VCC VCC VCC VCC VCC VCC 50 VCC VCC S S S S S S S S S S S S S 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 Notes: 1. On the ElanSC400 microcontroller only, the PC Card control signals for Socket A: The pullup resistors for the input signals are built in and can be disabled if external pullups are necessary (the external pullups can be on a different power plane). In Suspend mode, the signals can be configured for: a card not plugged in (inputs terminated with internal resistors), a card plugged in and powered (the output signals drive out inactive), a card plugged in and powered and at 5 V (the inactive High output signals are three-stated and pullup resistors should be put on the board), and a card plugged in and powered off (the signals terminated with pulldown resistors) (Power-Down Group G). Summary: The outputs are built-in pulldown resistors that are invoked by: -Suspend and PC Card Socket A is programmed to be powered off in Suspend (Power-Down Group G). -These are not pulldowns for normal operation. These are driven outputs. Summary: The inputs are built-in pullup and pulldown resistors that are invoked by: -Reset invokes pullups. -During normal operation, the pullup resistors can be disabled by a register bit. -During Suspend mode, the inputs will have pulldowns if the PC Card Socket A interface is programmed to be powered off in Suspend mode (Power-Down Group G). If the socket is not programmed to be powered off in Suspend mode, the inputs have the same state as when operating: the pullups are programmable to be enabled or not. 2. The PC Card signals MCEL_A, MCEH_A, RST_A, REG_A, CD_A, RDY_A, BVD1_A, BVD2_A, WP_A, WAIT_AB, OE, WE, and ICDIR are not supported on the ElanSC410 microcontroller. ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet 55 Table 16. Signal Name [Alternate Function] FRM [VL_LCLK] LC [VL_BE1] LCDD0 [VL_RST] LCDD1 [VL_ADS] LCDD2 [VL_W/R] LCDD3 [VL_M/IO] LCDD4 [VL_LRDY] LCDD5 [VL_D/C] LCDD6 [VL_LDEV] LCDD7 [VL_BE3] LVDD [VL_BLAST] LVEE [VL_BRDY] M [VL_BE2] SCK [VL_BE0] Pin # E19 E20 B20 C19 D18 C20 D19 E18 F17 D20 A19 A20 F18 F19 Type O [O] O [O] O [O] O [O] O [O] O [O] O [I] O [O] O [I] O [O] O [O] O [I] O [O] O [O] Pin State Table--Graphics Controller/VESA Local Bus Control Max Output Load Supply Drive (pF) E D D D D D D D D D D D D D 150 150 150 150 150 150 150 150 150 150 50 50 150 150 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Reset State TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PU TS-PU TS-PD TS-PD Normal Operation O[TS-PD] O[TS-PD] O[TS-PD] O[TS-PD] O[TS-PD] O[TS-PD] O[TS-PD] O[TS-PD] O[TS-PD] O[TS-PD] O[TS-PD] O[TS-PD] TS-PD[O] I O[TS-PD] O[TS-PD] TS-PD[O] I O[TS-PD] O[TS-PD] O[TS-PU] O[TS-PU] O[TS-PU] I O[TS-PD] O[TS-PD] O[TS-PD] O[TS-PD] Suspend State TS-PD TS-PD TS-PD H[TS-PD] TS-PD H[TS-PD] TS-PD H[TS-PD] TS-PD H[TS-PD] TS-PD H[TS-PD] TS-PD I[I-PD] TS-PD H[TS-PD] TS-PD I[I-PD] TS-PD H[TS-PD] H H[TS-PD] H I[I-PD] TS-PD H[TS-PD] TS-PD H[TS-PD] Power Down Group F 1,2 Note 1,2 5V S S S S S S S S S S F 1,2 F 1,2 F 1,2 F 1,2 F 1,2 F 1,2 F 1,2 F 1,2 F 1,2 F 1,2 F 1,2 S S F 1,2 F 56 ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet Notes: 1. The shared graphics controller interface and VESA local bus pins: These signals default to three-state with pulldown resistors and remain this way until an LCD or VL-bus interface is selected (all except LVEE and LVDD). When the graphics controller is enabled on the ElanSC400 microcontroller, the signals will be three-state with pulldowns whenever the LCD is not enabled. This allows the LCD to be powered off in any mode, and prevents damage to the LCD by having it powered when the timing of the signals is not correct. In Suspend these signals are three-state with pulldowns. The LCD cannot be driven in Suspend. When the VESA local bus interface is enabled, the signals will become the inputs and outputs necessary for VL-bus support. In Suspend, the signals support leaving the VL device powered on or off (Power-Down Group F). Summary: LCD control signals/VESA local bus control signals (all except LVEE and LVDD) have built-in pulldown resistors that are invoked by: -Reset invokes pulldowns. -Graphics controller disabled and VL-bus disabled invokes pulldowns. -VL-bus enabled and VL interface programmed for power-down in Suspend mode invokes pulldowns (Power-Down Group F). -Graphics controller enabled and LCD enabled. All pins are outputs with no termination. -Graphics controller enabled and LCD disabled. All pins are three-state with pulldowns. -VL-bus enabled and not Suspend mode. No pulldowns enabled. Summary: LVEE and LVDD have built-in pullup and pulldown resistors that are invoked by: -Reset invokes pullups. -VL-bus enabled and VL interface programmed for power-down in Suspend mode invokes pulldowns in Suspend mode (Power-Down Group F). -Graphics enabled. Drive out High in Suspend. -Graphics enabled. Both pins are outputs without pullups or pulldowns. -VL-bus enabled. No pullups or pulldowns in normal operation. 2. The graphics controller signals LCDD7-LCDD0, M, LC, SCK, FRM, LVEE, and LVDD are not supported on the ElanSC410 microcontroller. ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet 57 Table 17. Signal Name [Alternate Function] 32KXTAL1 32KXTAL2 ACIN BBATSEN BL1 BL2 BLO [CLK_IO] BNDSCN_EN LF_HS LF_INT LF_LS LF_VID RESET SPKR SUS_RES/ KBD_ROW14 Pin # Y6 Y4 W12 V6 Y13 W13 W14 Y11 V5 Y3 W4 W5 Y7 V7 Y12 STI A STI STI STI[B] I A A A A STI O STI/STI B 50 B 50 Type Pin State Table--Miscellaneous Reset State Normal Operation Suspend State Power Down Group Note 1 1 Max Output Load Supply Drive (pF) VRTC VRTC VCC VRTC VCC VCC VCC VCC AVCC AVCC AVCC AVCC VCC VCC VCC 5V I-PD I I I I I-PD Analog Analog Analog Analog I L I I-PD I I I I I[O] I-PD Analog Analog Analog Analog I O I I-PD I I I I I[TS-PD] I-PD Analog Analog Analog Analog I TS-PD I 2 1 1 Notes: 1. The 32-kHz crystal signals are active in all modes. The RESET signal is enabled as an input in all modes to reset the whole chip. The BBATSEN signal is active during reset to sense the state of the backup battery. Summary: No pullups or pulldowns on these pins. 2. The LF_VID signal is not supported on the ElanSC410 microcontroller. 58 ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet Table 18. GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin State Table--Power1 and Ground Pin # D4 D5 D6 D7 D8 D9 D10 D12 D11 E4 F4 G4 H4 H8 H9 H10 H11 H12 H13 J4 J8 J9 J10 J11 J12 J13 K8 K9 K10 K11 K12 K13 L8 L9 L10 L11 L12 L13 M8 M9 M10 M11 M12 Type -- -- -- -- -- -- -- -- -- -- -- -- -- Thermal Thermal Thermal Thermal Thermal Thermal -- Thermal Thermal Thermal Thermal Thermal Thermal Thermal Thermal Thermal Thermal Thermal Thermal Thermal Thermal Thermal Thermal Thermal Thermal Thermal Thermal Thermal Thermal Thermal Signal Name (Alternate Function) ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet 59 Table 18. GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND_A VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Pin State Table--Power1 and Ground (Continued) Pin # M13 N8 N9 N10 N11 N12 N13 R17 T17 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 Y5 A8 A13 A18 B1 B4 B16 E1 E17 G17 H1 J17 J3 L17 M1 M17 M19 N17 P17 P18 T1 U18 Type Thermal Thermal Thermal Thermal Thermal Thermal Thermal -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Analog I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Logic I/O Logic I/O Logic Logic I/O I/O I/O Signal Name (Alternate Function) 60 ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet Table 18. VCC VCC_RTC VCC VCC VCC VCC_A VCC_CPU VCC_CPU VCC_CPU VCC_CPU VCC_CPU VCC_CPU VCC_CPU Pin State Table--Power1 and Ground (Continued) Pin # V13 W7 W9 Y1 Y16 W6 K4 L4 M4 N4 P4 R4 T4 Type I/O RTC I/O I/O I/O Analog CPU CPU CPU CPU CPU CPU CPU Signal Name (Alternate Function) Notes: 1. See the signal descriptions under the Reset and Power subheading in the Signal Description table beginning on page 62 for additional information about the VCC pins. ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet 61 SIGNAL DESCRIPTIONS The descriptions in Table 19 are organized in alphabetical order within the functional group listed here. s System Interface on page 62 s Configuration Pins on page 63 s Memory Interface on page 64 s VL-Bus Interface on page 64 s Power Management on page 65 s Clocks on page 66 s Parallel Port on page 66 s Serial Port on page 66 s Keyboard Interfaces on page 67 s General-Purpose Input/Output on page 67 s Serial Infrared Port on page 67 s PC Card Controller (ElanSC400 Microcontroller Only) on page 67 s LCD Graphics Controller (ElanSC400 Microcontroller Only) on page 68 s Boundary Scan Test Interface on page 69 s Reset and Power on page 69 Table 19. Signal System Interface AEN O Type Description Signal Description Table DMA Address Enable indicates that the current address active on the SA25-SA0 address bus is a memory address, and that the current cycle is a DMA cycle. All I/O devices should use this signal in decoding their I/O addresses, and should not respond when this signal is asserted. When AEN is asserted, the PDACK1- PDACK0 signals are used to select the appropriate I/O device for the DMA transfer. AEN is also asserted when a DMA cycle is occurring internal to the chip. On the ElanSC400 microcontroller, AEN is also asserted for all accesses to the PC Card I/O space to prevent ISA devices from responding to the IOR/IOW signal assertions because these signals are shared between the PC Card and ISA interfaces. BALE O Bus Address Latch Enable is driven at the beginning of an ISA bus cycle with a valid address. This signal can be used by external devices to latch the address for the current cycle. BALE is also asserted for all accesses to the PC Card interfaces (memory or I/O) (ElanSC400 microcontroller only) and all DMA cycles. This prevents an ISA device from responding to a cycle based on a previously latched address. Data Buffer Output Enable controls the output enable on the external transceiver required to drive the peripheral data bus in local bus and 32-bit DRAM modes. High Byte Data Buffer Direction Control controls direction of data flow through the external transceiver required to drive the peripheral data bus in local bus and 32-bit DRAM mode. This is the control signal for the upper 8 bits of the data bus. Low Byte Data Buffer Direction Control controls direction of data flow through the external transceiver required to drive the peripheral data bus in local bus and 32-bit DRAM mode. This is the control signal for the lower 8 bits of the data bus. I/O Channel Ready should be driven by open-drain devices. When pulled Low during an ISA access, wait states are inserted in the current cycle. This pin has an internal weak pullup that should be supplemented by a stronger external pullup (usually 4.7 K to 1 K) for faster rise time. I/O Chip Select 16: The targeted I/O device drives this signal active early in the cycle to request a 16-bit transfer. I/O Read Command indicates that the current cycle is a read from the currently addressed I/O device. When this signal is asserted, the selected I/O device can drive data onto the data bus. This signal is also shared with the PC Card interface on the ElanSC400 microcontroller. I/O Write Command indicates that the current cycle is a write to the currently addressed I/O device. When this signal is asserted, the selected I/O device can latch data from the data bus. This signal is also shared with the PC Card interface on the ElanSC400 microcontroller. Memory Chip Select 16 indicates to the ISA control logic that the targeted memory device is a 16-bit-wide device. DBUFOE DBUFRDH O O DBUFRDL O IOCHRDY STI PU IOCS16 IOR I O IOW O MCS16 I 62 ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet Table 19. Signal MEMR Type O Description Signal Description Table (Continued) Memory Read Command indicates that the current cycle is a read of the currently addressed memory device. When this signal is asserted, the memory device can drive data onto the data bus. Memory Write Command indicates that the current cycle is a write of the currently addressed memory device. When this signal is asserted, the memory device can latch data from the data bus. Programmable DMA Acknowledge signals can each be mapped to one of the seven available DMA channels. They are driven active (Low) back to the DMA initiator to acknowledge the corresponding DMA requests. Programmable DMA Requests can each be mapped to one of the seven available DMA channels. They are asserted active (High) by a DMA initiator to request DMA service from the DMA controller. Programmable Interrupt Requests can each be mapped to one of the available 8259 interrupt channels. They are asserted when a peripheral requires interrupt service. (Rising Edge/Active High Trigger) System Reset is the ISA bus reset signal. When this signal is asserted, all connected devices reinitialize to their reset state. This signal should not be confused with the internal CPU RESET and SRESET signals. System Address Bus outputs the physical memory or I/O port latched addresses. It is used by all external peripheral devices other than main system DRAM. In addition, this is the local address bus in local bus mode. System Byte High Enable is driven active when the high data byte is to be transferred on the upper 8 bits of the ISA data bus. System Data Bus is shared between ISA, 8- or 16-bit ROM/Flash memory, and PC Card peripherals (on the ElanSC400 microcontroller only) and can be directly connected to all of these devices. In addition, these signals are the upper word of the local data bus, the 32-bit DRAM interface, and the 32-bit ROM interface. In these modes, the system data bus can be generated via an external buffer connected to the SD bus and controlled by the buffer control signals provided. Speaker, Digital Audio Output controls an external speaker driver. It is generated from the internal 8254-compatible timer Channel 2 output ANDed with I/O Port 0061h[1] (Speaker Data Enable); on the ElanSC400 microcontroller, the PC Card speaker signals are exclusively ORed with each other and the speaker control function of the timer to generate the SPKR signal. Terminal Count is driven from the DMA controller pair to indicate that the transfer count for the currently active DMA channel has reached zero, and that the current DMA cycle is the last transfer. Boundary Scan Enable enables the boundary scan pin functions. When this pin is High, the boundary scan interface is enabled. When this pin is Low, the boundary scan pin functions are disabled and the pins are configured to their default functions. This pin must be held Low during reset for normal operation. Configuration Pins 1-0 select the data bus width for the physical device(s) selected by the ROMCS0 pin (i.e., 8-, 16-, or 32-bit-wide). These pins are sampled at the deassertion of RESET. Configuration Pin 2 selects whether or not the system will boot from PC Card Socket A memory card or from the device attached to ROMCS0. This pin is sampled at the deassertion of RESET. This pin is not supported on the ElanSC410 microcontroller. Configuration Pin 3 enables the SD buffer control signals, DBUFOE, DBUFRDH, and DBUFRDL. This pin is sampled at the deassertion of RESET. MEMW O PDACK1-PDACK0 O PDRQ1-PDRQ0 I PIRQ7-PIRQ0 I RSTDRV O SA25-SA0 O SBHE SD15-SD0 O B SPKR O TC O Configuration Pins BNDSCN_EN I CFG1-CFG0 CFG2 I I CFG3 I ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet 63 Table 19. Signal Memory Interface CASH3-CASH0 O Type Description Signal Description Table (Continued) Column Address Strobe High indicates to the DRAM devices that a valid column address is asserted on the MA lines. These CAS signals are for the odd banks (Banks 1 and 3); CASH3-CASH2 are for the high word; and CASH1-CASH0 is for the low word. CASL3-CASL0 O Column Address Strobe Low indicates to the DRAM devices that a valid column address is asserted on the MA lines. These CAS signals are for the even banks (Banks 0 and 2); CASL1-CASL0 are for the low word; CASL3-CASL2 are for the high word. D31-D0 MA12-MA0 B O Data Bus is used for DRAM and local bus cycles. This bus is also used when interfacing to 32-bit ROMs. Memory Address: The DRAM row and column addresses are multiplexed onto this bus. Row addresses are driven onto this bus and are valid upon the falling edge of RAS. Column addresses are driven onto this bus and are valid upon the falling edge of CAS. Write Enable indicates an active write cycle to the DRAM devices. This signal is also used to three-state EDO DRAMs at the end of EDO read cycles. ROM 32-Bit Buffer Output Enable provides the buffer enable signal for the external transceivers on the low word of the ROM interface. This signal is automatically provided when the ROMCS0 interface is configured as 32 bit (the configuration can be done using either CFG1-CFG0 or CSC index 20h[1-0]). Once ROMCS0 is configured as 32 bit, all accesses to 32-bit ROM devices on ROMCS2-ROMCS0 result in the assertion of the R32BFOE signal. Row Address Strobe indicates to the DRAM devices that a valid row address is asserted on the MA lines. ROM Chip Selects are active Low outputs that provide the chip select for the BIOS ROM and/or the ROM/Flash memory array. After power-on reset, the ROMCS0 chip select will go active for accesses into the 64-Kbyte segment that contains the boot vector, at address 3FF0000h to 3FFFFFFh. ROMCS0 can be driven active during a linear (direct) address decode of certain addresses in the high memory (00A0000h-00FFFFFh) region. By default, direct-mapped accesses to the 64-Kbyte region from 00FFFF0h to 00FFFFFh are enabled to support Legacy PC/AT BIOS. This area is known as the aliased boot vector. It can also be activated by accessing a Memory Management System (MMS) page that points to the ROM0 address space. ROMCS1 is activated only when accessing an MMS page that points to it. A third, MMS-mappable ROMCS2 signal is available by reconfiguring one of the chip's General Purpose Input Output (GPIO) pins for this function and also requires the use of MMS to access devices connected to it. ROM Read indicates that the current cycle is a read of the currently selected ROM device. When this signal is asserted, the selected ROM device can drive data onto the data bus. ROM Write indicates that the current cycle is a write of the currently selected ROM device. When this signal is asserted, the selected ROM device can latch data from the data bus. Local Bus Address Strobe is asserted to indicate the start of a VL-bus cycle. It is always strobed Low for one clock period. The address and status lines are valid on the rising edge of VL_LCLK, which samples this signal Low. Local Bus Byte Enables indicate which byte lanes of the 32-bit data bus are involved with the current VL-bus transfer. Local Bus Burst Last is asserted to indicate that the next VL_BRDY assertion will terminate the current VL-bus transfer. MWE R32BFOE O O RAS3-RAS0 ROMCS2-ROMCS0 O O ROMRD ROMWR VL-Bus Interface VL_ADS O O O VL_BE3-VL_BE0 VL_BLAST O O 64 ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet Table 19. Signal VL_BRDY Type I Description Signal Description Table (Continued) Local Bus Burst Ready is asserted by the VL-bus target to indicate that it is terminating the current burst transfer. The chip samples this signal on the rising edge of VL_LCLK. VL_BRDY should be asserted for one VL_LCLK period per burst transfer. If VL_LRDY is asserted at the same time as VL_BRDY, VL_BRDY is ignored and the VL-bus transfer is terminated. Local Bus Data/Code Status is driven Low to indicate that code is being transferred. A High on this signal indicates that data is being transferred. Local Bus Memory/I/O Status is driven Low to indicate an I/O transfer. A High on this signal indicates a memory transfer. Local Bus Write/Read Status is driven Low to indicate a read transfer. A High on this signal indicates a write. Bus Cycle Initiated Interrupt Acknowledge Halt/Special Cycle I/O Read I/O Write Code Read Reserved Memory Read Memory Write VL_M/IO 0 0 0 0 1 1 1 1 VL_D/C 0 0 1 1 0 0 1 1 VL_W/R 0 1 0 1 0 1 0 1 VL_D/C VL_M/IO VL_W/R O O O VL_LCLK O Local Bus Clock is the VL-bus clock. It is used by the VL-bus target for all timing references. This signal is in phase with the internal CPU's clock input. (Rising Edge Active) Local Bus Device Select is asserted by the VL-bus target to indicate that it is accepting the current transfer as indicated by the address and status lines. The VL-bus target asserts this signal as a function of the address and status presented on the bus. Local Bus Ready is asserted by the VL-bus target to indicate that it is terminating the current bus cycle. This signal is sampled by the chip on the rising edge of VL_LCLK. Local Bus Reset is the VL-bus master reset. It is controlled with CSC index 14h[4]. AC Supply Active indicates to the system that it is being powered from an AC source. When asserted, this signal can disable power management functions (if configured to do so). Battery Low Detects indicate to the chip the current status of the system's primary battery pack. BL0-BL2 can indicate various conditions of the battery as conditions change. These inputs can be used to force the system into one of the power saving modes when activated (Low-going Edge). Latched Battery Low Detect 2 can be driven Low and latched on the low-going edge of the BL2 input to indicate to the system that the chip has been forced into the Suspend mode by a battery dead indication from the BL2 signal. It is cleared by one of the "all clear" indicators that allow the system to resume after a battery dead indication. Suspend/Resume Operation: When the chip is in Hyper-Speed, High-Speed, Low-Speed, or Standby mode, a software-configurable edge on this pin can cause the internal logic to enter Suspend mode. When in Suspend, a software-configurable edge on this pin can cause the chip to enter the High-Speed or Low-Speed mode. The choice of edge is configured using the SUS_RES Pin Configuration Register at CSC index 50h. VL_LDEV I VL_LRDY VL_RST Power Management ACIN BL2-BL0 I O I I LBL2 O SUS_RES I ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet 65 Table 19. Signal Clocks 32KXTAL1 32KXTAL2 CLK_IO I/O Type Description Signal Description Table (Continued) 32.768-kHz Crystal Interface Signals are used for the 32.768-kHz crystal. This is the main clock source for the chip and drives the internal Phase-Locked Loops (PLLs) that generate all other clock frequencies needed in the system. Clock Input/Output is an input to drive the integrated 8254 timer with a 1.19318-MHz clock signal from an external source, or an output to bring out certain internal clock sources to drive external devices. Loop Filters connect external RC loop filters required by the internal PLLs. LF_VID is not supported on the ElanSC410 microcontroller. Printer Acknowledge: In standard mode, this signal is driven by the parallel port device with the state of the printer acknowledge signal. In EPP mode, this signal indicates to the chip that the parallel port device has generated an interrupt request. Auto Line Feed Detect: In standard mode, this signal is driven by the chip indicating to the parallel port device to insert a line feed at the end of every line. In EPP mode, this signal is driven active by the chip during reads or writes to the EPP data registers. Printer Busy: In standard mode, this signal is driven by the parallel port device with the state of the printer busy signal. In EPP mode, this signal adds wait states to the current cycle. Error: The printer asserts this signal to inform the parallel port of a deselect condition, paper end (PE) or other error condition. Initialize Printer: This signals the printer to begin an initialization routine. Paper End: The printer asserts this signal when it is out of paper. Parallel Port Write Enable controls an external 374 type latch in a unidirectional parallel port design. This device latches the SD7-SD0 bus onto the parallel port data bus. To implement a bidirectional parallel port, this pin can be reconfigured to act as an address decode for the parallel port data port. PPDWE can then be externally gated with IOR and IOW to provide the Parallel Port Data Read and Write Strobes, respectively. Parallel Port Output Buffer Enable supports a bidirectional parallel port design. PPOEN controls the output enable of the external Parallel Port Output Buffer (373 octal D-type transparent latch). Printer Select is returned by a printer upon receipt of SLCTIN. Printer Selected: In Standard mode, this signal is driven by the chip to select the parallel port device. In EPP mode, this signal is driven active by the chip during reads or writes to the EPP address register. Strobe: In Standard mode, this signal indicates to the parallel port device to latch the data on the parallel port data bus. In EPP mode, this signal is driven active during writes to the EPP data or the EPP address register. Clear To Send is driven back to the serial port to indicate that the external data carrier equipment (DCE) is ready to accept data. Data Carrier Detect is driven back to the serial port from a piece of data carrier equipment when it has detected a carrier signal from a communications target. Data Set Ready indicates that the external DCE is ready to establish a communication link with the internal serial port controller. Data Terminal Ready indicates to the external DCE that the internal serial port controller is ready to communicate. Ring Indicate is used by an external modem to inform the serial port that a ring signal was detected. A change in state on this signal by the external modem can be configured to cause a modem status interrupt. This signal can be used to cause the chip to resume from a Suspend state. LF_INT, LF_LS, LF_VID, LF_HS ACK (INTR) A Parallel Port (Note: The names in parentheses in this section are those used in EPP mode.) I AFDT (DSTRB) O BUSY (WAIT) ERROR INIT PE PPDWE I I O I O PPOEN O SLCT SLCTIN (ASTRB) I O STRB (WRITE) O Serial Port CTS DCD DSR DTR RIN I I I O I 66 ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet Table 19. Signal RTS SIN SOUT Keyboard Interfaces KBD_COL7- KBD_COL0 KBD_ROW14- KBD_ROW0 XT_CLK XT_DATA O STI I/O I/O Type O I O Description Signal Description Table (Continued) Request To Send indicates to the external DCE that the internal serial port controller is ready to send data. Serial Data In receives the serial data from the external serial device or DCE into the internal serial port controller. Serial Data Out transmits the serial data from the internal serial port controller to the external serial device or DCE. Matrix-Scanned Keyboard Column Outputs drive the matrix keyboard column lines. (Open Collector Output with programmable termination) Matrix-Scanned Keyboard Row Inputs samples the row lines on the matrix keyboard. XT Keyboard Clock is the clock signal for an external XT keyboard interface. (Open Collector Output) XT Keyboard Data is the data signal for an external XT keyboard interface. (Open Collector Output) General Purpose I/Os and Programmable Chip Selects Each of the GPIOs can be programmed to be an input or an output. As outputs, all of the GPIOs can be programmed to be High or Low. Some of the GPIOs can be programmed to be High or Low for each of the power management modes. Also as outputs, some of these pins can be individually programmed as chip selects for other external peripheral devices. These can be configured as direct memory address decodes or I/O decodes qualified or non-qualified by the ISA bus command signals. Any one of the GPIO_CSx signals can be configured as ROMCS2. As inputs, all the GPIOs can be read back with a register bit. Some of these pins can be individually programmed to act as activity triggers, wake-up sources, or SMIs. General-Purpose Input/Output GPIO31-GPIO15 GPIO_CS14- GPIO_CS0 B Serial Infrared Port SIRIN SIROUT I O Infrared Serial Input is the digital input for the serial infrared interface. Infrared Serial Output is the digital output for the serial infrared interface. PC Card Controller (ElanSC400 Microcontroller Only) (Note: The names in parentheses in this section are those used in PC Card Memory and I/O mode.) BVD1_A (STSCHG_A)- BVD1_B (STSCHG_B) BVD2_A (SPKR_A) (DRQ_A)- BVD2_B (SPKR_B) (DRQ_B) I Battery Voltage Detect is driven Low by a PC Card when its on-board battery is dead. When the PC Card interface is configured for I/O, this signal can be driven by the card to indicate a card status change. It is typically used to generate a system IRQ in this mode. These signals are not supported on the ElanSC410 microcontroller. Battery Voltage Detect is driven Low by a PC Card when its on-board battery is weak. When the PC Card interface is configured for I/O, this signal can be driven by the card's speaker output. When enabled, this signal can drive the chip SPKR output. When PC Card DMA is enabled, the DMA request from the PC Card can be programmed to appear on this signal. See also the description for WP_A (IOIS16_A) (DRQ_A) and WP_B (IOIS16_B) (DRQ_B); the DMA request can also be programmed to appear on these pins. These signals are not supported on the ElanSC410 microcontroller. Card Detect indicates that the card is properly inserted. Socket A is capable of being configured to use two card detect inputs and Socket B is only provided with one. If only one card detect is to be used for a socket, the input signals should be driven from a logical AND (digital OR) of the CD1 and CD2 signals from their respective card interfaces. These signals are not supported on the ElanSC410 microcontroller. I CD_A-CD_B CD_A2 I ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet 67 Table 19. Signal ICDIR Type O Description Signal Description Table (Continued) Card Data Direction controls the direction of the card data buffers or voltage translators. It works with the MCEL and MCEH card enable signals to control data buffers on the card interface. When this signal is High, the data flow is from the chip to the card socket, indicating a data write cycle. When this signal is Low, the data flow is from the card socket into the chip, indicating a read cycle. This signal is not supported on the ElanSC410 microcontroller. Card Enables, High Byte enables a PC Card's high data bus byte transceivers for the respective card interfaces. These signals are not supported on the ElanSC410 microcontroller. Card Enables, Low Byte enables a PC Card's low data bus byte transceivers for the respective card interfaces. These signals are not supported on the ElanSC410 microcontroller. PC Card Output Enable: This is the PC Card memory read signal. This signal is not supported on the ElanSC410 microcontroller. PC Card Socket A VCC Enable can be used to control the VCC to Socket A. This signal is not supported on the ElanSC410 microcontroller. PC Card Socket A VPP Selects can be used to control the VPP to Socket A. These signals are not supported on the ElanSC410 microcontroller. PC Card Socket B VCC Enable can be used to control the VCC to Socket B. This signal is not supported on the ElanSC410 microcontroller. PC Card Socket B VPP Selects can be used to control the VPP to Socket B. These signals are not supported on the ElanSC410 microcontroller. Card Ready indicates that the respective card is ready to accept a new data transfer command. When the card interface is configured as an I/O interface, this signal is used as the card Interrupt Request input into the chip. These signals are not supported on the ElanSC410 microcontroller. Attribute Memory Select signals are driven inactive (High) for accesses to a PC Card's common memory, and asserted (Low) for accesses to a PC Card's attribute memory and I/O space for their respective card interfaces. When PC Card DMA is enabled, the DMA acknowledge to the PC Card appears on this signal. These signals are not supported on the ElanSC410 microcontroller. Card Reset signals are the reset for their respective cards. When active, this signal clears the Interrupt and General Control Register (PC Card index 03h and 43h), thus placing a card in an unconfigured (Memory-Only mode) state. It also indicates the beginning of any additional card initialization. These signals are not supported on the ElanSC410 microcontroller. Extend Bus Cycle delays the completion of the memory access or I/O access that is currently in progress. When this signal is asserted (Low), wait states are inserted into the cycle in progress. Only one WAIT input is provided on the chip. External logic is required for a two-socket implementation to logically AND (digitally OR) each card's WAIT signal together. This signal is not supported on the ElanSC410 microcontroller. PC Card Write Enable is the PC Card memory write signal. Data is transferred from the chip to the PC Card. When PC Card DMA is enabled, the DMA Terminal Count to the PC Card appears on this signal. This signal is not supported on the ElanSC410 microcontroller. Write Protect indicates the status of the respective card's Write Protect switch. When the respective card is configured for an I/O interface, this signal is used by the card to indicate back to the chip that the currently accessed port is 16 bits wide. When PC Card DMA is enabled, the DMA request from the PC Card can be programmed to appear on this signal. See also the description for BVD2_A (SPKR_A) (DRQ_A) and BVD2_B (SPKR_B) (DRQ_B); the DMA request can also be programmed to appear on these pins. These signals are not supported on the ElanSC410 microcontroller. LCD Panel Line Frame Start is asserted by the chip at the start of every frame to indicate to the LCD panel that the next data clocked out is intended for the start of the first scan line on the panel. Some panels refer to this signal as FLM or S (scan start-up). This signal is not supported on the ElanSC410 microcontroller. MCEH_A, MCEH_B MCEL_A, MCEL_B OE PCMA_VCC PCMA_VPP2- PCMA_VPP1 PCMB_VCC PCMB_VPP2- PCMB_VPP1 RDY_A (IREQ_A), RDY_B (IREQ_B) O O O O O O O I REG_A (DACK_A), REG_B (DACK_B) O RST_A, RST_B O WAIT_AB I WE (TC) O WP_A (IOIS16_A) (DRQ_A), WP_B (IOIS16_B) (DRQ_B) I LCD Graphics Controller (ElanSC400 Microcontroller Only) FRM O 68 ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet Table 19. Signal LC Type O Description Signal Description Table (Continued) LCD Panel Line Clock is activated at the start of every pixel line. It is commonly referred to by LCD data sheets as CL1 or CP1. This signal is not supported on the ElanSC410 microcontroller. LCD Panel Data bits: LCDD7-LCDD0 are data bits for the LCD panel interface. When driving 4-bit single-scan panels, bits 3-0 form a nibble-wide LCD data interface. In dual-scan panel mode, LCDD3-LCDD0 are the data bits for the top half of the LCD, and LCDD7- LCDD4 are the data bits for the bottom half of the LCD. When driving 8-bit single-scan panels (monochrome or color STN), these bits are the 8-bit data interface. These signals are not supported on the ElanSC410 microcontroller. LCD Panel VDD Voltage Control is used to control the assertion of the LCD's VDD voltage. This is provided to be part of the solution in sequencing the panel's VDD, DATA, and VEE in the proper order during panel power-up and power-down to prevent damage to the panel from CMOS driver latch up. VDD is used to power the LCD logic and is usually +5 V or +3 V DC. This signal is not supported on the ElanSC410 microcontroller. LCD Panel VEE Voltage Control is used to control the assertion of the LCD's VEE voltage. This is provided to be part of the solution in sequencing the panel's VDD, DATA, and VEE in the proper order during panel power-up and power-down to prevent damage to the panel from CMOS driver latch up. VEE is the LCD contrast voltage and is either positive or negative with an amplitude of 15-30 V DC.This signal is not supported on the ElanSC410 microcontroller. LCD Panel AC Modulation is the AC modulation signal for the LCD. AC modulation causes the LCD panel drivers to reverse polarity to prevent an internal DC bias from forming on the panel. This signal is not supported on the ElanSC410 microcontroller. LCD Panel Shift Clock is the nibble/byte strobe used by the LCD panel to latch a nibble or byte of incoming data. Commonly referred to by LCD panels as CL2 or CP2. This signal is not supported on the ElanSC410 microcontroller. Test Clock is the boundary-scan input clock that is used to shift serial data patterns in from BNDSCN_TDI. Test Data Input is the serial input stream for boundary-scan input data. This pin has a weak internal pullup resistor. It is sampled on the rising edge of BNDSCN_TCK. If not driven, this input is sampled High internally. Test Data Output is the serial output stream for boundary-scan result data. It is in the highimpedance state except when scanning is in progress. Test Mode Select is an input for controlling the test access port. This pin has a weak internal pullup resistor. If it is not driven, it is sampled High internally. Backup Battery Sense: RTC (Real Time Clock) backup battery voltage is sampled on this pin each time the AVCC pin has power applied to it followed by a chip master reset. If this samples below 2.4 V, the VRT bit (RTC index 0Dh) is cleared until read one time. At this time, the VRT bit is set until BBATSEN is sampled again. BBATSEN also provides a power-onreset signal for the RTC when an RTC backup battery is applied for the first time. Ground Pins Reset Input is an asynchronous hardware reset input equivalent to POWERGOOD in the AT system architecture. 3.3-V DC Supply Pins provide power to the discrete logic and I/O pins. 3.3-V Supply Pins provide power to the analog section of the chip, including the internal PLLs and integrated oscillator circuit. Extreme care should be taken that this supply voltage is isolated properly to provide a clean, noise free voltage to the PLLs. 3.3-V DC Supply Pins provide power to the internal CPU. 3.3-V Supply Pin provides power to the internal real-time clock and on-board static/ configuration RAM. This pin can be driven independently of all other power pins. LCDD7-LCDD0 O LVDD O LVEE O M O SCK O Boundary Scan Test Interface BNDSCN_TCK BNDSCN_TDI I I BNDSCN_TDO BNDSCN_TMS Reset and Power BBATSEN O TS I A GND RESET VCC VCC_A Analog I VCC_CPU VCC_RTC CPU RTC ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet 69 Multiplexed Pin Function Options Table 20 shows how to configure each multiplexed signal on the ElanSC400 and ElanSC410 microcontrollers. Note that those signals marked with a superscript 1 ( 1) are not supported on the ElanSC410 microcontroller. Pins with multiplexed functions have their functions selected in one of three ways: s By configuration pins that are latched during reset s By assertion at BNDSCN_EN s By firmware via programmed configuration registers Table 20. Signal You Want System Interface BALE DBUFOE DBUFRDH DBUFRDL MCS16 PDACK1 PDRQ1 PIRQ0 PIRQ1 PIRQ2 PIRQ3 PIRQ4 PIRQ5 PIRQ6 PIRQ7 R32BFOE Signals You Give Up KBD_ROW10 GPIO_CS4 GPIO_CS3 GPIO_CS2 KBD_ROW12 KBD_ROW7 KBD_ROW8 GPIO_CS8 GPIO_CS7 KBD_ROW9 KBD_COL2 KBD_COL3 KBD_COL4 KBD_COL5 KBD_COL6 KBD_ROW13 Multiplexed Pin Configuration Options How to Configure the Signal You Want on the Pin Pin # D2 C4 D17 C18 F3 D3 C2 W18 Y19 E3 A2 B3 C3 A1 B2 A3 Set CSC index 39h[2]. Hardwire strap the CFG3 pin High. Hardwire strap the CFG3 pin High. Hardwire strap the CFG3 pin High. Set CSC index 39h[2]. Set CSC index 39h[2]. Set CSC index 39h[2]. Set CSC index 38h[1]. Set CSC index 38h[2]. Set CSC index 39h[2]. Set CSC index 3Ah[1]. Set CSC index 3Ah[1]. Set CSC index 3Ah[2]. Set CSC index 3Ah[2]. Set CSC index 3Ah[2]. Hardwire-strap both the CFG1 and CFG0 pins High to enable the 32-bit ROM interface on ROMSC0. This automatically enables R32BFOE. SBHE KBD_ROW11 Set CSC index 39h[2]. Configuration Pins (Pinstraps) (See "Using the Configuration Pins to Select Pin Functions" on page 74.) Memory Interface CASH2 KBD_ROW2 Set bit 3 of the DRAM Bank x Configuration Register. Set CSC index 00h[7] and 00h[3], or KBD_ROW3 CASH3 Set CSC index 01h[7] and 01h[3], or CASL2 KBD_ROW0 Set CSC index 02h[7], or CASL3 KBD_ROW1 Set CSC index 03h[7]. MA12 KBD_ROW6 RAS2 KBD_ROW4 RAS3 KBD_ROW5 C1 C17 B18 B19 D16 B17 D15 C16 70 ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet Table 20. Multiplexed Pin Configuration Options (Continued) Signal You Want VL-Bus Interface VL_ADS VL_BE0 VL_BE1 VL_BE2 VL_BE3 VL_BLAST VL_BRDY VL_D/C VL_LCLK VL_LDEV VL_LRDY VL_M/IO VL_RST VL_W/R ISA Bus AEN IOCHRDY IOCS16 PDACK0 PDRQ0 TC GPIOs GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO21 GPIO22 GPIO23 GPIO24 GPIO25 GPIO26 GPIO27 GPIO28 GPIO29 GPIO30 GPIO31 GPIO_CS2 GPIO_CS3 GPIO_CS4 GPIO_CS5 GPIO_CS6 GPIO_CS7 GPIO_CS8 GPIO_CS9 GPIO_CS10 Signals You Give Up LCDD11 SCK1 LC1 M1 LCDD71 LVDD1 LVEE1 LCDD51 FRM1 LCDD61 LCDD41 LCDD31 LCDD01 LCDD21 GPIO_CS10 GPIO_CS6 GPIO_CS5 GPIO_CS11 GPIO_CS12 GPIO_CS9 PCMA_VPP21 PCMB_VCC1 PCMB_VPP11 PCMB_VPP21 LBL2 CD_A21 PPDWE PPOEN SLCT, WP_B1 BUSY, BVD2_B1 ACK, BVD1_B1 PE, RDY_B1 ERROR, CD_B1 INIT, REG_B1 SLCTIN, RST_B1 AFDT, MCEH_B1 STRB, MCEL_B1 DBUFRDL DBUFRDH DBUFOE IOCS16 IOCHRDY PIRQ1 PIRQ0 TC AEN How to Configure the Signal You Want on the Pin Enable the VL-bus interface by setting CSC index 14h[3]. Pin # C19 F19 E20 F18 D20 A19 A20 E18 E19 F17 D19 C20 B20 D18 V17 V18 W19 W17 Y17 Y18 Y15 V15 W15 Y14 V14 G18 V3 T3 U4 U3 U2 W2 V4 Y2 W3 W1 V2 C18 D17 C4 W19 V18 Y19 W18 Y18 V17 Set CSC index 38h[0]. Set CSC index 38h[3]. Set CSC index 38h[4]. Set CSC index 38h[0] Set CSC index 38h[0]. Set CSC index 38h[0]. Clear CSC index 39h[5]. Clear CSC index 39h[6]. Clear CSC index 39h[6]. Clear CSC index 39h[6]. Clear CSC index 39h[4]. Clear CSC index 3Ah[0]. Clear CSC index 39h[1-0]. Clear CSC index 39h[1-0]. Clear CSC index 39h[1-0]. Clear CSC index 39h[1-0]. Clear CSC index 39h[1-0]. Clear CSC index 39h[1-0]. Clear CSC index 39h[1-0]. Clear CSC index 39h[1-0]. Clear CSC index 39h[1-0]. Clear CSC index 39h[1-0]. Clear CSC index 39h[1-0]. Hardwire-strap the CFG3 pin Low. Hardwire-strap the CFG3 pin Low. Hardwire-strap the CFG3 pin Low. Clear CSC index 38h[4]. Clear CSC index 38h[3]. Clear CSC index 38h[2]. Clear CSC index 38h[1]. Clear CSC index 38h[0]. Clear CSC index 38h[0]. ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet 71 Table 20. Multiplexed Pin Configuration Options (Continued) Signal You Want Signals You Give Up GPIO_CS11 PDACK0 GPIO_CS12 PDRQ0 GPIO_CS13 PCMA_VCC1 GPIO_CS14 PCMA_VPP11 Parallel Port GPIO25, BVD1_B1 ACK AFDT GPIO30, MCEH_B1 BUSY GPIO24, BVD2_B1 GPIO27, CD_B1 ERROR INIT GPIO28, REG_B1 PE GPIO26, RDY_B1 GPIO21 PPDWE PPOEN GPIO22 SLCT GPIO23, WP_B1 GPIO29, RST_B1 SLCTIN STRB GPIO31, MCEL_B1 Keyboard Interface KBD_COL0 XT_DATA KBD_COL1 XT_CLK KBD_COL2 PIRQ3 KBD_COL3 PIRQ4 KBD_COL4 PIRQ5 KBD_COL5 PIRQ6 KBD_COL6 PIRQ7 KBD_ROW0 CASL2 KBD_ROW1 CASL3 KBD_ROW2 CASH2 KBD_ROW3 CASH3 KBD_ROW4 RAS2 KBD_ROW5 RAS3 KBD_ROW6 MA12 KBD_ROW7 PDACK1 KBD_ROW8 PDRQ1 KBD_ROW9 PIRQ2 KBD_ROW10 BALE KBD_ROW11 SBHE KBD_ROW12 MCS16 KBD_ROW13 R32BFOE How to Configure the Signal You Want on the Pin Clear CSC index 38h[0]. Clear CSC index 38h[0]. Clear CSC index 39h[5]. Clear CSC index 39h[5]. Write CSC index 39h[1-0] to 10. Pin # W17 Y17 V16 W16 U2 W1 U3 V4 Y2 W2 V3 T3 U4 W3 V2 E2 D1 A2 B3 C3 A1 B2 B19 D16 C17 B18 D15 C16 B17 D3 C2 E3 D2 C1 F3 A3 D1 E2 U2 U3 G18 V4 V14 N3 W1 P2 Clear CSC index 39h[3]. Clear CSC index 39h[3]. Clear CSC index 3Ah[1]. Clear CSC index 3Ah[1]. Clear CSC index 3Ah[1]. Clear CSC index 3Ah[1]. Clear CSC index 3Ah[1]. Clear CSC index 00h[7] and 00h[3], or clear CSC index 01h[7] and 01h[3], or clear CSC index 02h[7], or clear CSC index 03h[7]. Clear CSC index 39h[2]. Clear CSC index 39h[2]. Clear CSC index 39h[2]. Clear CSC index 39h[2]. Clear CSC index 39h[2]. Clear CSC index 39h[2]. Do not enable the 32-bit ROM interface on ROMCS0 (e.g., do not hardwire-strap both the CFG1 and CFG0 pins High). XT_CLK KBD_COL1 Clear CSC index 39h[3]. XT_DATA KBD_COL0 Clear CSC index 39h[3]. PC Card (ElanSC400 Microcontroller Only) BVD1_B1 GPIO25, ACK Write CSC index 39h[1-0] to 01. BVD2_B1 GPIO24, BUSY Write CSC index 39h[1-0] to 01. 1 CD_A2 GPIO20 Set CSC index 3Ah[0]. CD_B1 GPIO27, ERROR Write CSC index 39h[1-0] to 01. LBL21 GPIO19 Set CSC index 39h[4]. MCEH_A1 BNDSCN_TMS Pull the BNDSCN_EN pin Low. 1 MCEH_B GPIO30, AFDT Write CSC index 39h[1-0] to 01. MCEL_A1 BDNSCN_TCK Pull the BNDSCN_EN pin Low. 72 ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet Table 20. Multiplexed Pin Configuration Options (Continued) Signal You Want Signals You Give Up How to Configure the Signal You Want on the Pin MCEL_B1 GPIO31, STRB Write CSC index 39h[1-0] to 01. PCMA_VCC1 GPIO_CS13 Set CSC index 39h[5]. 1 GPIO_CS14 Set CSC index 39h[5]. PCMA_VPP1 PCMA_VPP21 GPIO15 Set CSC index 39h[5]. PCMB_VCC1 GPIO16 Set CSC index 39h[6]. GPIO17 Set CSC index 39h[6]. PCMB_VPP11 1 PCMB_VPP2 GPIO18 Set CSC index 39h[6]. RDY_B1 GPIO26, PE Write CSC index 39h[1-0] to 01. BNDSCN_TDO Pull the BNDSCN_EN pin Low. REG_A1 REG_B1 GPIO28, INIT Write CSC index 39h[1-0] to 01. 1 RST_A BNDSCN_TDI Pull the BNDSCN_EN pin Low. GPIO29, SLCTIN Write CSC index 39h[1-0] to 01. RST_B1 WP_B1 GPIO23, SLCT Write CSC index 39h[1-0] to 01. LCD Graphics Controller (ElanSC400 Microcontroller Only) FRM1 VL_LCLK Enable the graphics controller by setting CSC index DDh[2]. LC1 VL_BE1 LCDD01 VL_RST LCDD11 VL_ADS 1 LCDD2 VL_W/R LCDD31 VL_M/IO LCDD41 VL_LRDY LCDD51 VL_D/C 1 LCDD6 VL_LDEV LCDD71 VL_BE3 VL_BLAST LVDD1 LVEE1 VL_BRDY 1 M VL_BE2 SCK1 VL_BE0 Boundary Scan Interface BDNSCN_TCK MCEL_A 1 Pull the BNDSCN_EN signal High. 1 BNDSCN_TDI RST_A BNDSCN_TDO REG_A1 BNDSCN_TMS MCEH_A 1 Miscellaneous BL0 CLK_IO Write CSC index 38h[7-6] to 01. CLK_IO BL0 Write CSC index 38h[7-6] to 10 to enable CLK_IO as an output or to 11 to enable CLK_IO as a timer clock input. Pin # V2 V16 W16 Y15 V15 W15 Y14 W2 M2 Y2 R1 W3 U4 E19 E20 B20 C19 D18 C20 D19 E18 F17 D20 A19 A20 F18 F19 P2 R1 M2 N3 W14 W14 Notes: 1. This signal is not supported on the ElanSC410 microcontroller. ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet 73 Using the Configuration Pins to Select Pin Functions The configuration pins are used only for those functions that must be selected at reset, prior to firmware execution. All other I/O functions are selected using configuration registers. Table 21 provides an overview of the configuration pin functions. All of the CFG pins have weak internal pulldown resistors that select the default function. External pullup resistors are required to select an alternative function. Table 21. Pinstrap Bus Buffer Options ROMCS0 DBUFOE Data DBUFRDL R32BFOE DBUFRDH Width x8 x16 x32 x8 x16 x32 2 2 Table 22. CFG1 0 0 1 1 CFG0 and CFG1 Configuration CFG0 0 1 0 1 Configuration x8 ROMCS0 ROM interface Reserved x16 ROMCS0 ROM interface x32 ROMCS0 ROM interface CFG2 Pin--ElanSC400 Microcontroller Only This configuration pin (see Table 23) is used on the ElanSC400 microcontroller to select the ROMCS0 steering at system boot time. The boot ROM chip select (ROMCS0) can either be enabled to drive the ROMCS0 pin or can be rerouted to drive the PC Card (Socket A only) interface chip selects. The CFG0 and CFG1 pins are still used to select the data bus width for the ROMCS0 decode, regardless of the CFG2 configuration. The PC Card ROMCS0 redirection should not be selected when the CFG0 and CFG1 configuration pins are set to select a x32 ROM interface. When the ROM chip select decode has been redirected to PC Card Socket A, all of the normal PC Card controller features can still be used to drive the PC Card Socket A interface. The ROM chip select decode remapping to the PC Card socket can be enabled and disabled using firmware at any time. Table 23. CFG2 0 1 CFG3 CFG1 CFG0 (1) 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Disabled Disabled Disabled Enabled Enabled Enabled Disabled Reserved Disabled Enabled Disabled Reserved Disabled Enabled Reserved Reserved Reserved Reserved Notes: 1. CFG3 is defined as the enable/disable for the DBUFOE, DBUFRDL, and DBUFRDH signals. They can be enabled independently of whether a x32 D bus is selected via the firmware to support the VL local bus or x32 DRAM interface. 2. The x32 ROM option must be selected for ROMCS0 for the R32BFOE signal to be enabled. The selection of the DBUFOE, DBUFRDL, and DBUFRDH signals are still dependent only on the CFG3 signal. CFG2 Configuration (ElanSC400 microcontroller only) Configuration Enables the ROMCS0 decode on the ROMCS0 pin Enables the ROMCS0 decode to access PC Card Socket A CFG0 and CFG1 Pins These pins (shown in Table 22) configure the data bus width (x8, x16, or x32) of the ROM interface that is selected by the ROMCS0 pin. If a x32 ROM is selected, these pins also enable the ROM x32 Data Bus Buffer Output Enable signal (R32BFOE). If a 32-bit data bus width is selected for the ROM interface, the R32BFOE signal will be asserted for all ROMCSx accesses to 32-bit ROM. Exercise caution because the data bus width for the ROMCS0 interface can also be changed through programming. This feature was implemented mainly for testing. . 74 ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet CFG3 Pin This configuration pin is used for selecting between the GPIO_CS4-GPIO_CS2 I/O pins and the SD bus buffer control signals: DBUFOE, DBUFRDL, and DBUFRDH. When the buffer control signal configuration is selected using the CFG3 pin, the DBUFOE, DBUFRDL, and DBUFRDH signals are driven from boot time on for all accesses to the peripheral data bus. These signals are used for the external system bus transceiver control. See Table 24 for the CFG3 configuration definitions. Table 24. CFG3 Configuration CFG3 0 1 Configuration Enables the GPIO_CS4-GPIO_CS2 signals on the I/O pins Enables the SD bus buffer control signals DBUFOE, DBUFRDL, and DBUFRDH on the I/O pins BNDSCN_EN Pin The BNDSCN_EN configuration pin (see Table 25) is used to enable the boundary scan function I/O pins. The following pins are configured for their boundary scan function when BNDSCN_EN is asserted: s BNDSCN_TCK s BNDSCN_TMS s BNDSCN_TDI s BNDSCN_TDO Table 25. BNDSCN_EN 0 1 BNDSCN_EN Configuration Configuration Enables the PC Card function Enables the boundary scan functions: BNDSCN_TCK, BNDSCN_TMS, BNDSCN_TDI, and BNDSCN_TDO ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet 75 CLOCKING Clock Generation The ElanSC400 and ElanSC410 microcontrollers require only one 32.768-kHz crystal to generate all the other clock frequencies required by the system. The output of the on-chip crystal oscillator circuit is used to generate the various frequencies by utilizing four Phase-Locked Loop (PLL) circuits. The PLL clock distribution scheme is shown in Figure 4. Table 26 shows all the PLL output frequencies and their usage. (Note that these four PLL circuits are in addition to the internal CPU PLL and do not replace it.) The crystal oscillator needs two pins, but it does not require any external components except the crystal; the load capacitors and the feedback resistor are integrated on-chip. The four PLLs are called Intermediate PLL, Low-Speed PLL, High-Speed PLL, and Graphics Dot Clock PLL. Each of the integrated phase-locked loops has a dedicated pin to support the required external loop filter. These pins are: LF_INT (Intermediate PLL), LF_LS (Low-Speed PLL), LF_HS (High-Speed PLL), and LF_VID (Graphics Dot Clock PLL). (The LF_VID pin is not supported on the ElanSC410 microcontroller.) Two capacitors and one resistor are required to implement each loop filter. 32.768-kHz Crystal Oscillator 32.768 kHz Real-Time Clock PMU Intermediate PLL 1.47456 MHz DRAM Controller 36.864 MHz Divisors UART Timer Graphics Controller DRAM Controller Divisors ISA Bus DMA Controller CPU and VL-Bus Controller ROM/Flash Interface PC Card Controller Low-Speed PLL Graphics Dot Clock PLL High-Speed PLL 66.3552 MHz 20.736- 36.864 MHz Notes: On the ElanSC400 microcontroller, the graphics controller's DRAM interface is clocked by the 66-MHz DRAM clock. Both the ROM/Flash memory interface and the PC Card controller are clocked from the CPU clock. They also have the option to be run from the slow system clock. Neither the graphics controller nor the PC Card controller are supported on the ElanSC410 microcontroller. Figure 4. Clock Generation Block Diagram 76 ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet Integrated Peripheral Clock Sources Table 26 and Figure 5 show the primary peripheral clocks internal to the microcontroller and the PLL and divider sources that are used in the generation of these clocks. Note that several of the peripheral clocks are programmable. This programmability is either directly controlled by system firmware or is forced due to a power-management mode change. The graphics controller and the PC Card controller are not supported on the ElanSC410 microcontroller. Table 26. Integrated Peripheral Clock Sources Source PLL Intermediate PLL 1.4746 MHz Low-speed PLL 36.864 MHz Divider 1 1 20 2 31 Graphics dot clock PLL 36.864 MHz High-speed PLL 66.3552 MHz Programmable 1 1 2 4 Resulting Frequency 1.4746 MHz 36.864 MHz 1.8432 MHz 18.4328 MHz 1.1892 MHz 20.736-36.864 MHz 36.864 MHz 66.3552 MHz 33.1776 MHz 16.5888 MHz Where Used Low-speed PLL input High-speed PLL input Graphics dot clock PLL input UART UART PIT Graphics controller dot clock Graphics controller DRAM controller Graphics controller CPU VL-bus controller CPU VL-bus controller DMA controller CPU VL-bus controller ISA bus controller ROM/Flash memory interface DMA controller PC Card controller CPU VL-bus controller ISA bus controller ROM/Flash memory interface DMA controller PC Card controller CPU VL-bus controller ISA bus controller ROM/Flash memory interface DMA controller PC Card controller CPU VL-bus controller ISA bus controller ROM/Flash memory interface DMA controller PC Card controller 8 8.2944 MHz 16 4.1472 MHz 32 2.0736 MHz 64 1.0368 MHz ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet 77 32.768 kHz 32.768 kHz Enable Enable PMU Enable Oscillator Intermediate PLL Low-Speed PLL Graphics Dot Clock PLL 32.768 kHz 1.4746 MHz 36.864 MHz 20.736 MHz- 36.864 MHz RTC DRAM Controller and PMU Enable Graphics Controller Dot Clock High-Speed PLL 66.3552 MHz Graphics Dot Clock Select PLL Block /2 /20 18.432 MHz 1.8432 MHz UART CLK_IO CLK_IO Select /31 CLK_IO 1.1892 MHz 1.19318 MHz Timer 36.864 MHz 66.3552 MHz /2 /4 /8 /16 /32 /64 DRAM Clock Select CPU Clock Select ISA Bus Clock Select DMA Clock Select 33.1776 MHz 16.5888 MHz 8.2944 MHz 4.1472 MHz 2.0736 MHz 1.0368 MHz DRAM and Graphics Controllers CPU and VL-Bus Controller ISA Bus, ROM, and PC Card Controllers DMA Controller Notes: The graphics controller and the PC Card controller are not supported on the ElanSC410 microcontroller. Figure 5. 78 Clock Source Block Diagram ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet 32-kHz Crystal Oscillator The 32-kHz oscillator circuit is shown in Figure 6; the only external component required for operation is a 32.768-kHz crystal. The inverting amplifier (AMP) is integrated on-chip together with the feedback resistor and the load capacitors. As shown in Figure 7, the onchip oscillator circuit can be bypassed by removing the external crystal, grounding the 32KXTAL1 pin, and driving the 32KXTAL2 pin with an external 32-kHz clock. (The 32KXTAL2 pin should not exceed 2.0 V.) When 32KXTAL1 is grounded, the amplifier no longer affects the circuit. For an even cleaner circuit, the designer could optionally place an analog VCC power plane directly under the loop filter circuit. The value of the loop filter parameters can also affect the performance of the filter. For example, the values of C1 and R affect lock time and jitter (increasing RC increases lock time and decreases jitter). The value of C2 can help clean up high-frequency noise. Note that using too large of values for the components can cause the PLL to become unstable. The loop filter component value specifications are shown in Table 28 on page 84. Intermediate and Low-Speed PLLs Figure 8 on page 80 shows the block diagram for both the Intermediate and Low-Speed PLLs. Each consists of a phase detector, a charge pump, a voltage controlled oscillator (VCO), an external loop filter, and a feedback divider. This is a generic implementation of the charge-pump PLL architecture; all four PLLs use the same architecture. The Intermediate and LowSpeed PLLs differ only in component values and frequency of operation. The phase detector compares the phase and frequency of the two clock signals, reference frequency (Fr) and feedback frequency (Ff). The Up signal is a logic 1 if Fr leads Ff, while the Down signal is a logic 1 if Ff leads Fr. The Up and Down signals control the charge pump. The charge pump either charges or discharges the loop filter capacitors to change the VCO input voltage level. Because the VCO output frequency tracks the VCO input voltage, the VCO output frequency is adjusted whenever Fr and Ff differ in phase or frequency. The feedback divide ratio determines the frequency multiplication factor. Frequency multiplication is 1/(Feedback Divider). AMP Internal External 32KXTAL1 32KXTAL2 32.768-kHz Crystal Figure 6. 32-kHz Crystal Circuit 32 kHz Oscillator 32KXTAL1 Pin #Y4 2 V 32KXTAL2 max Figure 7. 32-kHz Oscillator Circuit Loop Filters Each of the PLLs in the ElanSC400 and ElanSC410 microcontrollers requires an external loop filter. For a cleaner circuit, the designer should consider the following: s Place the loop filter components as close as possible to the loop filter signals (LF_INT, LF_LS, LF_HS, and LF_VID (ElanSC400 microcontroller only)), which are located in one corner of the microcontroller. s Route the loop filter signals first and by hand. s Keep all clocks and noisy signals away from the loop filter area (even on the inner layers). For the Intermediate PLL, the feedback divider is 1/45; therefore, the frequency multiplication is 45. With an input frequency of 32.768 kHz, the output frequency is 1.47456 MHz. The input clock for the Low-Speed PLL, Fr, originates at the Intermediate PLL output. Fr is multiplied by 25 to generate the 36.864-MHz clock output. ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet 79 VCCA Reference Frequency (Fr) Up Phase Detector Down Charge Pump C1 Feedback Frequency (Ff) R C2 Loop Filter Divider VCO Vc Frequency Output (Fo) Internal External Figure 8. Intermediate and Low-Speed PLLs Block Diagram Graphics Dot Clock PLL (ElanSC400 Microcontroller Only) The input clock to the Graphics Dot Clock PLL is the output clock (36.864 MHz) of the Low-Speed PLL divided by 16. The Graphics Dot Clock PLL is not supported on the ElanSC410 microcontroller. The output frequency is programmable using three extended register bits (PLLRATIO[2-0]) in the range of 20.736 MHz to 36.864 MHz (spaced 2.304 MHz apart). These three bits (in graphics index register 4Ch) control the output Table 27. Frequency Selection Control for Graphics Dot Clock PLL Divider 9 10 11 12 13 14 15 16 Output Frequency (MHz) 20.736 23.04 25.344 27.648 29.952 32.256 34.56 36.864 frequency by selecting the divide value in the feedback divider as shown in Table 27. The Graphics Dot Clock PLL requires a stabilization period after changing frequency. Figure 9 shows the block diagram for the Graphics Dot Clock PLL. PLLRATIO[2-0] 000 001 010 011 100 101 110 111 80 ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet VCCA Fr 36.864 MHz /16 Phase Detector Up Down Charge Pump Loop Filter C1 Ff PLLRATIO[2-0] R C2 Programmable Divider (9-16) Fo VCO 20.736- 36.864 MHz Vc Internal External Figure 9. Graphics Dot Clock PLL Block Diagram High-Speed PLL The High-Speed PLL generates a 66.3552-MHz clock for the DRAM controller. Figure 10 on page 82 shows the block diagram for the High-Speed PLL. The input to the High-Speed PLL is the output of the Low-Speed PLL divided by five. The feedback divider is nine, which results in an output frequency (Fo) of 66.3552 MHz. This frequency is divided by 2 in the PMU to provide the 33-MHz input for the PLL in the CPU core. RTC Voltage Monitor The voltage monitor for the RTC block is shown in Figure 11 on page 82. Its functions are to provide a reset signal to the RTC block when it detects a low backup battery voltage, and to provide an early warning signal when the system is powering down. The internal RTC reset signal is asserted on power-up if the back-up battery voltage drops below 2.4 V. The one shot prevents multiple resets during power-on. An internal power-down signal is used by the RTC to isolate the RTC core from the rest of the microcontroller. The RTC voltage monitor uses the RESET assertion to detect a power-down. For proper operation, RESET and VCC must follow the timing in Figure 12 on page 83. Band Gap Block The band gap reference circuit generates the bias currents for the four PLLs and provides a 2.4-V reference source for the RTC voltage monitor. The current sources, constant over VCC, temperature, and process variations, are used by the four PLL charge pumps for adjusting the PLL operating frequency. The 2.4-V reference voltage is used by the RTC voltage monitor to detect a low backup battery voltage level. ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet 81 VCCA Fr 36.864 MHz /5 Ff Phase Detector Down Up Charge Pump C1 R C2 Loop Filter Fo Divider (9) 66.3552 MHz VCO Vc Internal External Figure 10. High-Speed PLL Block Diagram BBATSEN - One Band Gap Voltage Shot RTC Reset + RESET D Q Internal RTC Power-Down Flip Flop 32 kHz CK Figure 11. RTC Voltage Monitor Circuit 82 ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet RESET 3.3 V 2.7 V VCC 33 s (min) 32 kHz Notes: 1. These timings apply only when powering down the chip while leaving only the RTC powered. 2. Applies to all VCC except for the VCC_RTC, which is left on for this mode. 3. Guarantees at least one rising edge after reset before 2.7 volts is reached. Figure 12. Timing Diagram for RTC-On Power-Down Sequence Clock Specifications The specifications for the external components required to implement the four PLL loop filters are shown in Table 28 on page 84. Table 29 on page 84 lists the electrical specifications for the analog VCC (VCCA) pin. The on-chip crystal oscillator circuit supports most generic 32.768-kHz crystals as long as the specification for the crystals meet the electrical parameters listed in Table 30 on page 84. The worst-case start-up time required for the PLLs is shown in Table 31 on page 84. The PLL jitter specification is listed in Table 32 on page 85. Programmable Interval Timer (PIT) The ElanSC400 and ElanSC410 microcontrollers are equipped with a Programmable Interval Timer (PIT) that is software-compatible with PC/AT 8254 system timers. Historically, the clock source for this timer has been 1.19318 MHz. However, the internal PIT clock source is 1.1892 MHz. The user has two options: s Use the internal PIT clock source (1.1892 MHz), which can adversely affect the Legacy software that depends on the 1.19318-MHz frequency. s Drive an external 1.19318-MHz clock onto the CLK_IO pin and program this signal to be the source of the PIT clock. For more details on this feature, refer to the subsection on configuring Timer Channel 0 in the programmable i n t e r v a l ti m e r s e c t i o n o f t h e E l a n S C4 0 0 a n d ElanSC410 Microcontrollers User's Manual, order #21030. ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet 83 Table 28. Loop-Filter Component Specification for PLLs Parameter C1 C2 R Intermediate PLL 0.01 F 0.001 F 4.7 K Low-Speed PLL 470 pF 22 pF 4.7 K Graphics Dot Clock PLL 470 pF 33 pF 4.7 K High-Speed PLL 330 pF 15 pF 4.7 K Tolerance 10% 10% 10% Table 29. Analog VCC (VCCA) Specification Parameter Peak-to-peak noise on VCCA Current consumption in High-Speed mode Current consumption in Low-Speed mode Current consumption in Standby mode Current consumption in Suspend mode (PLLs off) 2 2 2 1 1 Min Typ Max 75 Unit mV mA mA mA A Notes: 1. 2 mA if PLLs are enabled. Table 30. 32.768-kHz Crystal Characteristics Parameter Nominal frequency Load capacitance Q value Series resistance Insulation resistance Shunt capacitance 100 2.5 13.5 50 60 Min Typ 32.768 15 16.5 Max Unit kHz pF 103 K M pF Table 31. Start-Up Time Specifications PLLs Symbol t1 t2 t3 t4 Parameter Intermediate PLL lock Low-Speed PLL lock High-Speed PLL lock Graphics Dot Clock PLL lock Min Typ Max 10 100 100 100 Unit ms s s s 84 ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet RESET (Wakeup) t1 Intermediate PLL Lock t2 Low-Speed PLL Lock High-Speed PLL Lock t3 t4 PLLRATIO[2:0] Graphics Dot Clock PLL Lock Figure 13. PLL Enabling Timing Sequence Table 32. PLL Intermediate PLL frequency Intermediate PLL cycle-to-cycle jitter Low-Speed PLL frequency Low-Speed PLL cycle-to-cycle jitter Graphics Dot Clock PLL frequency Graphics Dot Clock PLL cycle-to-cycle jitter High-Speed PLL frequency High-Speed PLL cycle-to-cycle jitter PLL Jitter Specification Min 1.4524 36.311 -1.5% 65.360 Typ 1.47456 36.864 Target 66.3552 Max 1.4967 20.4 37.417 0.82 +1.5% 1 67.351 0.5 Unit MHz ns MHz ns MHz ns MHz ns ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet 85 ABSOLUTE MAXIMUM RATINGS Storage Temperature . . . . . . . . . . . . -65C to +125C Ambient Temperature Under Bias . . -65C to +110C Supply Voltage VCC with Respect to GND . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to +4.6 V Voltage on 5-V-Tolerant Pins . . -0.5 V to (VCC +2.6 V) Voltage on Other Pins . . . . . . . -0.5 V to (VCC +0.5 V) Stresses above those listed may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. OPERATING RANGES Commercial (C) Devices Ambient Temperature (TA) Operating in Free Air. . . . . . . . . . . . . . . .0C to +70C Supply Voltage (VCC) . . . . . . . . . . . . +3.0 V to +3.6 V CPU Voltage (VCC_CPU) (33 & 66 MHz) +2.7 V to +3.6 V CPU Voltage (VCC_CPU) (100 MHz) +3.3 V to +3.6 V Operating ranges define those limits between which the functionality of the device is guaranteed. DC CHARACTERISTICS OVER COMMERCIAL AND INDUSTRIAL OPERATING RANGES (BALL GRID ARRAY (BGA), 33 MHZ, 3.3 V)1 Symbol fOSC PCC PCCSS2 Parameter Description Frequency of Operation (internal CPU clock) Supply Power--CPU clock = 33 MHz (VCC_CPU=3.3 V) Suspend Power at 3.3 V and 25C--CPU idle, all internal clocks stopped except 32.768 kHz Suspend Power at 3.3 V and 70C--CPU idle, all internal clocks stopped except 32.768 kHz POFF VOH(CMOS) VOL(CMOS) VIH(CMOS) VIH(5-VTOL) VIL(CMOS) ILI IIH IIL ILO AVCCRP-P RTC Power Only at 3.3 V Output High Voltage IOH(CMOS) = -0.5 mA Output Low Voltage IOL(CMOS) = +0.5 mA Input High Voltage Input High Voltage (5-V tolerant inputs) Input Low Voltage Input Leakage Current (0.1 V VOUT VCC) (All pins except those with internal pullup/pulldown resistors) Input Leakage Current (VIH = VCC - 0.1 V) (All pins with internal pulldown resistors) Input Leakage Current (VIL = 0.1 V) (Pins with internal pullup resistors) Output Leakage Current (0.1 V VOUT VCC) (All pins except those with internal pullup/pulldown resistors) Analog VCC ripple peak to peak 2.03 2.03 -0.3 VCC - 0.45 0.45 VCC +0.3 VCC +2.5 +0.8 10 60 -60 15 100 Min 0 703 264 (80 A) 726 (220 A) 16 Typ Max 100 879 643.5 (195 A) 1950.5 (585 A) 33 Unit MHz mW W W W V V V V V A A A A mV Notes: 1. VCCIO = 3.0 V-3.6 V. For 33 and 66 MHz, TCASE = 0C to +95C (commercial). TCASE = -40C to +95C (industrial). For 100 MHz, TCASE = 0C to +85C (commercial). Current out of a pin is given as a negative value. 2. In Suspend and Critical Suspend, the power state is the same. The PLLs are off, the LCD is disabled, and the CPU and all logic are in the lowest power state. The power management unit is active. 3. VCC at 3.3 V. 86 ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet Table 33. Power Pin Type Analog CPU RTC VCC Min 2.7 2.7 2.7 2.7 Operating Voltage (Commercial and Industrial) 33 MHz Max 3.6 3.6 3.6 3.6 Min 2.7 2.7 2.7 2.7 66 MHz Max 3.6 3.6 3.6 3.6 Min 2.7 3.3 2.7 2.7 100 MHz Max 3.6 3.6 3.6 3.6 CAPACITANCE Symbol CIN COUT CI/O Parameter Descriptions Input Capacitance Clock Capacitance Output Capacitance I/O Pin Capacitance Test Conditions FC = 1 MHz Min Max 15 15 20 20 Unit pF pF pF pF Notes: These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet 87 TYPICAL POWER NUMBERS Power Requirements Under Different Power Management Modes Table 34 shows the maximum and typical power dissipation for the ElanSC400 and ElanSC410 microcontrollers. Table 34. Power Estimates Power Management Mode (CPU Clock Speed) Hyper-Speed (100 MHz) Maximum at 3.3 V Typical at 3.3 V Maximum at 2.7 V Typical at 2.7 V 2194 mW (~665 mA) 1818 mW (551 mA) N/A N/A 1 Hyper-Speed1 (66 MHz) 1527 mW (~463 mA) 1222 mW (~370 mA) 941 mW 753 mW High-Speed2 (33 MHz) 879 mW (~266 mA) 703 mW (~213 mA) 586 mW 469 mW Low-Speed3 (~4 MHz) 240 mW (~73 mA) 192 mW (~58 mA) 144 mW 115 mW Standby4 (0 MHz) 63 mW (~19 mA) 50 mW (~15 mA) 60 mW 48 mW Off5 33 W (10 A) 16 W (4.8 A) 33 W 16 W Notes: 1. Hyper-Speed mode is defined with a CPU clock frequency of 66 or 100 MHz. There is a time penalty to engage and disengage Hyper-Speed mode, because a CPU Stop Clock/Stop Grant sequence is required to "arbitrate" the internal CPU PLL startup, cache flush, and the clearing of all internal pipelines and write buffers. The DX2 mode (66 MHz) is a clock-doubled mode with the CPU operating at 66 MHz and the rest of the system logic operating at 33 MHz. The DX4 mode (100 MHz) is a clock tripled mode with the CPU running at 100 MHz and the rest of the system running at 33 MHz. 2. High-Speed mode is defined with a maximum CPU clock speed of 33 MHz with a 1x dynamic clock-speed change control capability. Dynamic clock control allows fast, unarbitrated CPU clock-speed changes. Table 34 assumes a CPU frequency of 33 MHz and that the internal LCD controller is enabled. Other High-Speed mode power estimates with CPU VCC = 3.3 V are shown below: CPU Clock = 33 MHz/2 = 16.5 MHz, Max = 601 mW, Typical = 480 mW CPU Clock = 33 MHz/4 = 8.25 MHz, Max = 370 mW, Typical = 296 mW 3. Low-Speed mode limits the maximum CPU clock frequency to 8 MHz. Table 34 assumes 8 MHz/2 = ~4.125 (CPU speed) and that the Internal LCD controller is enabled. Other Low-Speed power estimates with CPU at 3.3 V are shown below: 8 MHz/1 = 8.25 MHz, Max = 370 mW, Typical = 296 mW 8 MHz/4 = 2.06 MHz, Max = 164 mW, Typical = 132 mW 4. Standby mode is defined as having the CPU idle and stopped (0 MHz), but video screen refresh continues. IRQ0 (DOS Timer IRQ source) is assumed to be programmed as an activity and is generated at a rate of 60 Hz. This causes the PMU to transition to the Temporary Low-Speed mode where the CPU is clocked at 8 MHz. The assumed duration of the IRQ0 handler routine is 25 s and, upon the interrupt return instruction, the PMU immediately re-enters the Standby mode, the LCD controller is enabled, and DRAM refresh type is slow CAS-before-RAS. 5. Off is defined as the VCC_RTC supply pin having power applied and all other VCC pins are not powered. In this mode, the core CPU, power management unit, PLLs, etc. have no power applied. The RTC will have an internally isolated power plane and source its power from the VCC_RTC supply pin. 88 ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet DERATING CURVES This section describes how to use the derating curves on the following pages to determine potential specified timing variations based on system capacitive loading. The Pin State Tables beginning on page 42 in this document have a column named "Max Load." This column describes the specification load presented to the specific pin when testing was performed to generate the timing specification documented in the AC Characteristics section of this data sheet. For example, to find out the effect of capacitive loading on a DRAM specification such as MWE hold from CAS Low, first find the specification load for MWE from Table 7 on page 44. The value here is 70 pF. Note the output drive type is programmable to C, D, or E. For this example, assume a drive strength of D, a system DRAM interface of 3.3 V, and a system load on the microcontroller's MWE pin of 90 pF. Referring to Figure 20, 3.3-V I/O Drive Type D Rise Time, on page 90, a time value of approximately 8.1 ns corresponds to a capacitive load of 70 pF. Also referring to Figure 20, a time value of approximately 10 ns corresponds to a capacitive load of 90 pF. Subtracting 8.1 ns from the 10 ns, it can be seen that the rise time on the MWE signal will increase by 1.9 ns. Therefore, the MWE hold from CAS Low (min) parameter will increase from 30 ns to 31.9 ns (30 ns +1.9 ns). If the capacitive load on MWE had been less than 70 pF, the time given in the derating curve for the load would be subtracted from the time given for the specification load. This difference can then be subtracted from the MWE hold from CAS Low (min) parameter to determine the derated AC timing parameter. 100 90 80 Time (ns) 70 60 50 40 30 20 10 20 40 60 80 100 Load (pF) 120 140 160 100 90 80 70 Time (ns) 60 50 40 30 20 10 20 40 60 80 100 Load (pF) 120 140 160 Figure 14. 3.3-V I/O Drive Type A Rise Time Figure 15. 3.3-V I/O Drive Type A Fall Time 50 45 40 35 Time (ns) 30 25 20 15 10 5 20 40 60 80 100 Load (pF) 120 140 160 Time (ns) 50 45 40 35 30 25 20 15 10 5 20 40 60 80 100 Load (pF) 120 140 160 Figure 16. 3.3-V I/O Drive Type B Rise Time Figure 17. 3.3-V I/O Drive Type B Fall Time ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet 89 30 25 Time (ns) Time (ns) 40 60 80 100 Load (pF) 120 140 160 20 15 10 5 20 30 25 20 15 10 5 20 40 60 80 100 Load (pF) 120 140 160 Figure 18. 3.3-V I/O Drive Type C Rise Time Figure 19. 3.3-V I/O Drive Type C Fall Time 18 16 14 Time (ns) Time (ns) 40 60 80 100 Load (pF) 120 140 160 12 10 8 6 4 2 20 18 16 14 12 10 8 6 4 2 20 40 60 80 100 Load (pF) 120 140 160 Figure 20. 3.3-V I/O Drive Type D Rise Time Figure 21. 3.3-V I/O Drive Type D Fall Time 13 12 11 10 9 8 7 6 5 4 3 2 20 40 60 80 100 Load (pF) 120 140 160 13 12 11 10 9 8 7 6 5 4 3 2 20 Time (ns) Time (ns) 40 60 80 100 Load (pF) 120 140 160 Figure 22. 3.3-V I/O Drive Type E Rise Time Figure 23. 3.3-V I/O Drive Type E Fall Time 90 ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet AC SWITCHING CHARACTERISTICS AND WAVEFORMS The AC specifications provided in the AC characteristics tables that follow consist of output delays, input setup requirements, and input hold requirements. AC specifications measurement is defined by the figures that follow each timing table. All timings are referenced to 1.5 V unless otherwise specified. Output delays are specified with minimum and maximum limits, measured as shown. The minimum delay times are hold times provided to external circuitry. Input setup and hold times are specified as minimums, defining the smallest acceptable sampling window. Within the sampling window, a synchronous input signal must be stable for correct microcontroller operation. Key to Switching Waveforms WAVEFORMS INPUTS Must be Steady OUTPUTS Will be Steady May Change from H to L Will be Changing from H to L May Change from L to H Will be Changing from L to H Don't Care, Any Change Permitted Changing, State Unknown Does Not Apply Center Line is High-Impedance "Off" State AC SWITCHING TEST WAVEFORMS VIH = VCC VCC / 2 Test Points VCC / 2 VIL = 0 Input Output Notes: For AC testing, inputs are driven at 3 V for a logic 1 and 0 V for a logic 0. ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet 91 AC Switching Characteristics over Commercial and Industrial Operating Ranges Table 35. Power-On Reset Cycle Symbol t1 t2 t3 t4 t5 t6 Parameter Description VCC_RTC valid hold before all other VCCs are valid RESET valid hold from all VCC valid (except VCC_RTC) VCC_RTC valid to BBATSEN active CFGx setup to RESET inactive CFGx hold from RESET inactive RSTDRV pulse width 1 Notes 33-MHz External Bus Min 0 0.5 100 5 0 300 Typ Max Unit s s s s ns ms Notes: 1. This parameter is dependent on the 32-kHz oscillator start-up time, which is dependent on the characteristics of the crystal, leakage and capacitive coupling on the board, and ambient temperature. VCC_RTC t1 All VCCs t2 RESET t3 BBATSEN t6 RSTDRV t4 CFGx t5 Figure 24. Power-Up Timing Sequence 92 ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet Table 36. ROM/Flash Memory Cycles Symbol t1 t2a t2b t2c t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16a t16b t17a t17b t18 t19 t20 t21a t21b t22 t23 t24a t24b t25 t26 t27 t28 t29 Parameter Description SA3-SA0 delay from SA31-SA4 SA stable to ROMCSx assertion SA stable to ROMCSx assertion when qualified with command (ROMRD or ROMWR) SA stable to ROMCSx assertion when qualified with command (ROMRD or ROMWR) ROMCSx deassertion to SA change SD setup to ROMRD or ROMCSx deassertion or burst address switching, whichever is first, for 8-/16-/32-bit device ROMWR setup to ROMCSx Data hold from SA, ROMRD, or ROMCSx change, whichever is first ROMCSx pulse width DBUFOE, R32BFOE setup to ROMRD, ROMWR Low ROMRD pulse width SA3-SA0 burst address valid duration ROMWR pulse width SD setup to ROMWR assertion for 32-bit device SD hold from ROMWR deassertion SA hold from ROMWR deassertion ROMRD delay from SA stable ROMRD, ROMWR pulse width for 8-bit device ROMRD, ROMWR pulse width for 16-bit device Data setup from ROMRD for 8-bit device Data setup from ROMRD for 16-bit device ROMRD deassertion to SA unstable Data hold from ROMRD deassertion SA hold from ROMWR deassertion SD setup to ROMWR assertion for 16-bit device SD setup to ROMWR assertion for 8-bit device SD hold from ROMWR deassertion IOCHRDY assertion to ROMRD, ROMWR deassertion IOCHRDY deassertion from ROMRD, ROMWR for 8-bit IOCHRDY deassertion from ROMRD, ROMWR for 16-bit R32BFOE/DBUFOE hold from ROMRD High R32BFOE/DBUFOE hold from ROMWR High DBUFRDL, DBUFRDH setup to ROMRD, ROMWR Low DBUFRDL, DBUFRDH hold from ROMRD High DBUFRDL, DBUFRDH hold from ROMWR high 0 26 0 26 -8 2 2 2 2 2, 4 2, 4 3 3 3 2 2 2 2 3 1 1 Notes 33-MHz External Bus Min Max 6 6 20 100 53 15 0 0 25 -8 25 25 25 17 20 20 115 530 240 489 209 20 0 53 -29 33 26 125 378 66 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1 1 2 ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet 93 Notes: 1. The ROMCSx address decode is programmable for an early decode (via bit 5 in CSC index 23h, 25h, and 27h). The early address-decode is available to provide the ROMCSx by qualifying the address signals only; it is not qualified with the commands (ROMRD, ROMWR). The timing parameter t2a pertains to the early address-decode feature being enabled (ROMCSx is address-decode only). Parameters t2b and t2c are observed when the early address-decode feature is disabled (ROMCSx is address-decode qualified with command). The early decode can be enabled for both Fast-mode and Normal-mode ROM accesses. 2. When a x32 DRAM or VL bus is enabled, additional delay must be added to accommodate for the delay through the external data buffers required for the SD bus in this mode. 3. There are two types of programmable wait states. The first programmable wait state is always used in the first access for either burst or non-burst supported device. It starts at the assertion of the chip select or at the transition of SA3-SA0, whic hever occurs later. The second programmable wait state is used only for any subsequent burst read accesses to a burst mode ROM device. It starts at the transition of SA3-SA0. The burst address valid duration depends on which wait state is used. If the wait state is set to zero, then the minimum address duration is 30 ns (one bus clock cycle). 4. If wait states are added via the deassertion of IOCHRDY, the data setup time to IOCHRDY assertion is 0 ns (minimum). t2b SA25-SA4 t1 t1 SA3-SA0 ROMCSx ROMWR t28 t6 t25 t7 t4 t6 t27 ROMRD SD15-SD0 D15-D0 (x32 ROM) DBUFOE R32BFOE DBUFRDH DBUFRDL t8 t9 Figure 25. Fast Mode 8-/16-/32-Bit ROM/Flash Memory Read Cycle 94 ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet t2b SA25-SA4 t6 t1 SA3-SA0 ROMCSx ROMWR 3 * t9 t2a t4 t10 t1 0 1 2 ROMRD SD7-SD0 Notes: The ROM controller fetches the number of bytes requested by the CPU as dictated by the CPU BE (Byte Enable) signals and returns the data as a single transfer. In this example, BE was set to "0001". Therefore, the ROM controller generates additional addresses to read all three bytes before returning them to the CPU. Figure 26. Fast Mode CPU Read of Three Consecutive Bytes from 8-Bit ROM/Flash Memory t2b SA25-SA0 ROMCSx t2a t5 t14 ROMWR ROMRD SD15-SD0 D15-D0 (x32 ROM) DBUFOE R32BFOE DBUFRDL DBUFRDH t27 t8 t11 t12 t13 t29 t26 Figure 27. Fast Mode 8-/16-/32-Bit Flash Memory Write Cycles ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet 95 t2b SA25-SA4 t4 t1 SA3-SA1 ROMCSx ROMWR 8 x t9 t2a 8 * t7 t10 t6 t1 ROMRD SD15-SD0 Figure 28. Fast Mode 16-Bit Burst ROM Read Cycles t2b SA25-SA4 t4 t1 SA3-SA2 ROMCSx ROMWR t27 t8 ROMRD SD15-SD0 DBUFOE R32BFOE DBUFRDL DBUFRDH 4 * t9 t28 t25 t2a 4 * t7 t10 t6 t1 Figure 29. Fast Mode CPU Burst Read from 32-Bit Burst Mode ROM/Flash Memory 96 ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet t15 t2c SA25-SA4 t1 SA3-SA0 ROMCSx t2a t23 t3 t18 t1 ROMRD ROMWR SD15-SD0 DBUFOE R32BFOE IOCHRDY DBUFRDL DBUFRDH t8 t27 t16a,b t17a,b t24a,b t28 t25 t19 Figure 30. Normal Mode 8-/16-Bit ROM/Flash Memory Read Cycles t20 SA25-SA4 t1 SA3-SA0 ROMCSx t2a t1 t27 t8 ROMWR ROMRD SD15-SD0 DBUFOE R32BFOE DBUFRDL DBUFRDH IOCHRDY t21a,b t24a,b t16a,b t23 t29 t22 t26 Figure 31. Normal Mode 8-/16-Bit Flash Memory Write Cycles ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet 97 Table 37. Symbol t1 t2 t3 t4 t5 t6a t6a t6b t7a t7b t8a t8b t9a t9b t9c t10 t11 t12a t12b t13 t14a t14b t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 t26 t27 t28 t29 t30 t31 t32 t33 Parameter Description DRAM Cycles Notes 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Row address setup time RAS to CAS delay Row address hold time Column address setup time Column address hold time CAS pulse width (CPU, Fast Page mode) CAS pulse width (graphics controller, Fast Page mode) CAS pulse width (EDO mode) CAS precharge (non-interleaved) CAS precharge (interleaved) CAS hold CAS hold (EDO) Fast page mode cycle time (non-interleaved) Fast page mode cycle time (interleaved) EDO mode cycle time Access time from RAS Access time from column address Access time from CAS Access time from CAS (EDO) Access time from CAS precharge Read data hold from CAS Read data hold from CAS (EDO) MA12-MA0 switching time Delay between bank CAS signals MWE setup to CAS MWE hold from CAS Write data setup to CAS Write data hold from CAS RAS precharge RAS pulse width RAS hold MWE low from CAS (EDO data disable) MWE pulse width (EDO) Data high impedance from MWE RAS to CAS precharge time CAS setup time (CAS-before-RAS refresh) CAS hold time (CAS-before-RAS refresh) RAS pulse width during self-refresh cycle RAS precharge time during self-refresh cycle WE setup time (CAS-before-RAS refresh) WE hold time (CAS-before-RAS refresh) 33-MHz External Bus Min Max 5 42.75 14.25 0 14.25 42.75 28.5 28.5 14.25 71.25 85.5 66.5 57 114 57 66.5 35 20 22 40 0 5 15 15 10 30 10 30 60 75 28.5 14.25 14.25 15 15 10 25 100 130 25 25 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns us ns ns ns Notes: 1. All timings assume 70-ns DRAMs, fastest programmable timing, and a 66-MHz clock for the memory controller. 98 ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet t1 RAS t8a t4 CASL3-CASL0 t2 t6a t7b t16 t6a t9b t16 CASH3-CASH0 t4 t6a t3 t15 MA12-MA0 MWE t5 t15 t12a t11 t10 D31-D0 t14a t12a t11 Figure 32. DRAM Page Hit Read, Interleaved t1 RAS t2 t8a t17 t4 t19 t9b t6a t7b t6a CASL3- CASL0 t16 CASH3- CASH0 t3 t15 MA12-MA0 t18 t5 t15 t6a t7b t9b t6a MWE t20 D31-D0 t20 Figure 33. DRAM Page Hit Write, Interleaved ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet 99 t1 t21 RAS t8a t4 CASL3-CASL0 t2 t6a t22 t23 t16 t6a CASH3-CASH0 t3 t15 MA12-MA0 MWE t12a t11 t10 D31-D0 t14a t5 t12a Figure 34. DRAM Page Miss Read, Interleaved t1 RAS t8a t4 t4 CASH3-CASH0 CASL3-CASL0 t2 t6a t7a t9a t6a t3 t15 MA12-MA0 MWE t5 t15 t12a t11 t10 D31-D0 t13 t12a t14a Figure 35. DRAM Page Hit Read, Non-Interleaved 100 ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet t1 RAS t2 t8a t19 t4 CASH3-CASH0 CASL3-CASL0 t3 t15 MA12-MA0 t18 MWE t20 D31-D0 t15 t5 t17 t6a t7a t9a t6a Figure 36. DRAM Page Hit Write, Non-Interleaved t1 t21 RAS t8a t22 t23 t9a t4 CASH3-CASH0 CASL3-CASL0 t2 t6a t7a t6a t3 t15 MA12-MA0 MWE t5 t15 t12a t11 t10 D31-D0 t12a t14a t13 Figure 37. DRAM Page Miss Read, Non-Interleaved ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet 101 t1 RAS t8b t4 CASH3-CASH0 CASL3-CASL0 t2 t6b t9c t7a t6b t3 t15 MA12-MA0 t5 t15 t24 t25 MWE t12b t11 t10 D31-D0 t13 t12b t14b t11 t26 Notes: The EDO DRAM page hit write timing is similar to DRAM page hit write timing. See Figure 36 on page 101 for more information. Figure 38. EDO DRAM Page Hit Read, Non-Interleaved t1 t21 RAS t8b t4 CASH3-CASH0 CASL3-CASL0 t2 t22 t6b t3 t15 MA12-MA0 t5 t24 MWE t25 t12b t11 t10 D31-D0 t26 Notes: The EDO DRAM page miss write timing is similar to DRAM page miss write timing. See Figure 36 on page 101 for more information. Figure 39. EDO DRAM Page Miss Read, Non-Interleaved 102 ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet clk_mem t27 t27 t28 t27 t27 t7a CASH3-CASH0 CASL3-CASL0 t33 t32 RAS0 t33 t32 RAS1 t33 t32 RAS2 t33 t32 RAS3 MWE t22 t22 t22 t22 t28 t28 t28 t29 t29 t29 t29 t7a t27 t27 t27 t27 Figure 40. DRAM CAS-Before-RAS Refresh t7a t27 t28 CASH3-CASH0 CASL3-CASL0 t21 RAS MWE SS t30 SS 7a t27 t31 Notes: Because the sequence shown above is performed when the microcontroller is in Suspend mode, the DRAMs must self-refresh. The RAS and CAS signals are held active (Low) for the entire time that the microcontroller is in Suspend mode. The timing diagram also shows a following cycle that brings RAS and CAS High again. The Low period of RAS and CAS can be of a long duration. Figure 41. DRAM Self-Refresh ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet 103 t27 t28 t7a CASH3-CASH0 CASL3-CASL0 t33 t32 RAS0 t33 t22 RAS1 t33 t22 RAS2 t33 t22 RAS3 MWE t22 t29 Notes: The diagram above shows RAS and CAS behavior for an ElanSC400 or ElanSC410 microcontroller running at a frequency of 16 MHz or less. In this case, the RAS signals are not staggered and all are driven (Low) at the same time to consume less DRAM bandwidth for refresh activity (consumed due to a slower clock frequency). Figure 42. DRAM Slow Refresh 104 ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet Table 38. ISA Cycles Symbol t1a t1b t2a t2b t3a t3b t3c t3d t3e t3f t3g t3h t4 t5a t5b t6 t7a t7b t8 t9 t11a t11b t12 t13a t13b t13c t14 t15 t16 t17 t19 t20 t21 t22a t22b t23 t24 t25 t26 t27 Parameter Description Setup, SA, SBHE stable to command assertion, 16-bit I/O, 8-bit I/O, Mem Setup, SA, SBHE stable to command assertion, 16-bit Mem Delay, MCS16 stable from SA Delay, IOCS16 stable from SA Pulse width, IOW, 8-bit cycle Pulse width, MEMW, 8-bit cycle Pulse width, IOR, 8-bit cycle Pulse width, MEMR, 8-bit cycle Pulse width, IOW, 16-bit cycle Pulse width, MEMW, 16-bit cycle Pulse width, IOR, 16-bit cycle Pulse width, MEMR, 16-bit cycle SA, SBHE hold from command deassertion IOCHRDY delay from IOR, MEMR, IOW, MEMW (8-bit) IOCHRDY delay from IOR, MEMR, IOW, MEMW (16-bit) IOR, MEMR, IOW, MEMW delay from IOCHRDY IOR, MEMR, IOW, MEMW high time (8-bit) IOR, MEMR, IOW, MEMW high time (16-bit) Delay, BALE rising from IOR, MEMR, IOW, MEMW deassertion IOCHRDY pulse width Setup, SD to write command assertion, 8-bit memory, I/O write and 16-bit I/O write Setup, SD to write command assertion, 16-bit memory write Hold, SD from write command deassertion Data access time, 8-bit read Data access time, 16-bit I/O read Data access time, 16-bit memory read Hold, SD from read command deassertion Setup, SA, SBHE stable to BALE falling edge Pulse width, BALE Setup, AEN high to IOR/IOW assertion Setup, SA, SBHE stable to command assertion Hold, DRQ from DACK assertion Setup, DACK assertion to I/O command assertion Setup, IOR assertion to MEMW command Setup, MEMR command assertion to IOW command Delay, IOCHRDY assertion to command high Delay, memory command to IOCHRDY deassertion Hold, command off to DACK off Hold, read command off from write command off Hold, AEN from command off 60 50 60 0 61 60 145 102 0 145 235 0 200 125 125 187 125 46 120 ns 15.6 s 33 -29 30 489 132 209 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 530 530 530 530 165 240 165 240 53 378 66 Notes 33-MHz External Bus Min 120 120 102 122 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet 105 Table 38. ISA Cycles (Continued) Symbol t29 t30 t31 t32a t32b t33a t33b t34 t35 t36 t37 t38 t39 t41 t42 t43 t44 t45 t46 t47 t48 t49 t50 t51 t52 t53 t54 t55 t56 Parameter Description Hold, SA, SBHE from read command Setup, TC to read command deassertion Hold, TC from read command deassertion Pulse width, I/O write command Pulse width, I/O read command Pulse width, memory read command Pulse width, memory write command Delay, MEMR to valid data Hold, SD from MEMR deassertion Delay, IOR to valid data Hold, SD from IOR deassertion Setup, SD to MEMW assertion Setup, SD to IOW assertion Setup, DBUFRDL/DBUFRDH to write command Low Hold, DBUFRDL/DBUFRDH from write command High Setup, DBUFRDL/DBUFRDH to read command Low Hold, DBUFRDL/DBUFRDH from read command High Setup, DBUFOE Low to write command Low Hold, DBUFOE from write command High Setup, DBUFOE Low to read command Low Hold, DBUFOE from read command High Setup, DBUFRDL/DBUFRDH to mem read command Low, DMA Hold, DBUFRDL/DBUFRDH from mem read command High, DMA Setup, DBUFOE Low to mem read command Low, DMA Hold, DBUFOE from mem read command High, DMA Setup, DBUFRDL/DBUFRDH to I/O read command Low, DMA Setup, DBUFOE Low to I/O read command Low, DMA Hold, DBUFOE from I/O read command High, DMA Hold, DBUFRDL/DBUFRDH from I/O read command High, DMA 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Notes 33-MHz External Bus Min 53 470 60 400 700 800 470 272 11 241 11 -21 -214 45 30 0 10 45 30 0 10 0 10 0 10 0 0 10 10 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes: 1. These parameters are applicable only when an external data transceiver is used to isolate the SD bus. 106 ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet t1a SA25-SA0, SBHE t41 t45 t11a t5a t3a,b t4 t6 t12 t46 t42 t1a t4 IOW/MEMW t13a t3c,d t6 t14 t47 t43 t5a t7a t44 t48 IOR/MEMR IOCHRDY SD7-SD0 (Write) SD7-SD0 (Read) DBUFRDL DBUFOE t9 Figure 43. 8-Bit ISA Bus Cycles ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet 107 t2a,b t2a,b t1a,b t15 SA25-SA0, SBHE t16 BALE t41 t11a,b t45 t5b t3e,f t4 t6 t46 t42 t16 t2a,b t1a,b t15 t4 IOW/MEMW t5b t3g,h t6 t43 t47 t13b,c t14 t44 t48 t7b IOR/MEMR t9 IOCS16/MCS16 IOCHRDY DBUFRDL DBUFRDH DBUFOE SD15-SD0 (Write) SD15-SD0 (Read) Figure 44. 16-Bit ISA Bus Cycles 108 ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet t20 PDRQx PDACKx t21 t25 t19 SA25-SA0, SBHE t17 AEN t22b t24 t39 t32a IOW t23 t49 t51 t33a t34 t29 t27 t26 MEMR t31 t30 t52 t35 t50 SD15-SD0 IOCHRDY TC DBUFRDL DBUFRDH DBUFOE Figure 45. ISA DMA Read Cycle ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet 109 t20 PDRQx PDACKx t21 t25 t19 SA23-SA0, SBHE t17 AEN t22a t24 t38 t33b t29 t27 MEMW t26 t23 t30 t53 t54 t36 t32b IOR SD15-SD0 IOCHRDY t31 t55 t37 t56 TC DBUFRDL DBUFRDH DBUFOE Figure 46. ISA DMA Write Cycle 110 ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet Table 39. Symbol t1 t2 t3 t4 t5 t6 t7 t81 t9 t10 t11 t12 t13 t14 Parameter Description VL_LCLK period VL_LCLK pulse High VL_LCLK pulse Low VL_ADS delay from VL_LCLK VESA Local Bus Cycles 33-MHz External Bus Min 27 14 14 3 3 3 18 18 18 20 15 12 0 0 5 0 3 18 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit SA25-SA2, VL_BE3-VL_BE0, VL_M/IO, VL_W/R, VL_D/C delay from VL_LCLK VL_BLAST valid from VL_LCLK VL_LDEV valid from SA25-SA2, VL_BE3-VL_BE0, VL_M/IO, VL_W/R, VL_D/C VL_LDEV setup to VL_LCLK VL_LRDY, VL_BRDY setup to VL_LCLK VL_LRDY, VL_BRDY (VL-Bus target is driver) hold from VL_LCLK VL_LRDY (VL-Bus target is driver) three stated from VL_LCLK Read data setup to VL_LCLK Read data hold from VL_CLK Write data delay from VL_CLK Notes: 1. LDEV is checked on the following rising edge of the CPU clock (not shown, up to 100 MHz) from the assertion of ADS. ADS can assert a minimum of 20 ns after address change. ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet 111 t3 t1 t2 VL_LCLK CPUADS1 t9 t8 t12 t9 t12 t4 VL_ADS t5 SA25-SA2, VL_BE t7 VL_LDEV t13 Read Data t14 t14 Write Data t10 VL_LRDY t10 t11 t7 t5 t4 t13 t14 t10 VL_BRDY t6 VL_BLAST t6 t6 t11 Notes: 1. This signal is shown as a timing reference only. It is not available as a pin on the ElanSC400 microcontroller. Figure 47. VESA Local Bus Cycles 112 ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet Table 40. Parallel Port Cycles1 Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 Parameter Description PPDWE delay from IOW PPOEN delay from IOW STRB delay from IOW SLCTIN, AFDT valid from IOW SD setup to IOW SD hold from IOW BUSY asserted from IOW asserted IOW deasserted from BUSY deasserted IOW pulse width SLCTIN, AFDT recovery DBUFOE setup to IOW DBUFOE hold from IOW PPDWE delay from IOR SLCTIN, AFDT valid from IOR SD setup to IOR deasserted SD hold from IOR BUSY asserted from IOR asserted IOR deasserted from BUSY deasserted IOR pulse width DBUFOE, DBUFRDL setup to IOR DBUFOE, DBUFRDL hold from IOR 5 5 4 4 5 5 2 3 4 4 3 Notes 2 33-MHz External Bus Min 2 2 2 2 50 50 300 100 450 1000 20 20 2 2 20 0 300 100 450 0 10 20 20 Max 20 20 20 20 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes: 1. The signal names used in Figure 48 and Figure 49 are the PC/AT Compatible and Bidirectional mode signal names. 2. During EPP mode and Bidirectional mode, PPDWE acts as the parallel port chip select and is asserted for both reads and writes. For PC/AT Compatible mode, PPDWE will be asserted only for parallel port write cycles. 3. These timings are only valid for EPP mode. 4. BUSY is asserted to add wait states to the parallel port access. 5. DBUFOE and DBUFRDL may be required when using the VESA local bus interface or a x32 DRAM interface. ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet 113 . t5 IOW t11 t9 t8 PPDWE t1 t1 t2 PPOEN t3 t3 t2 STRB SLCTIN t4 Address Register Access t4 t4 t10 t4 Data Register Access t6 t10 AFDT SD7-SD0 t7 BUSY DBUFOE DBUFRDL t12 Figure 48. EPP Parallel Port Write Cycle 114 ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet t19 t15 t18 IOR t13 t13 PPDWE PPOEN STRB SLCTIN t14 Address Register Access t14 Data Register Access t14 t10 AFDT t14 t10 t16 SD7-SD0 BUSY t17 t21 DBUFOE DBUFRDL t20 Figure 49. EPP Parallel Port Read Cycle Table 41. Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 Parameter Description SA stable to GPIO_CSx rising edge SA stable to GPIO_CSx falling edge IOW rising edge to GPIO_CSx rising edge IOW falling edge to GPIO_CSx falling edge IOR rising edge to GPIO_CSx rising edge IOR falling edge to GPIO_CSx falling edge SA stable to GPIO_CSx (8042CS) falling edge SA stable to GPIO_CSx (8042CS) rising edge SA stable to GPIO_CSx (MEMCS) falling edge SA stable to GPIO_CSx (MEMCS) rising edge MEMW rising edge to GPIO_CSx rising edge MEMW falling edge to GPIO_CSx falling edge MEMR rising edge to GPIO_CSx rising edge MEMR falling edge to GPIO_CSx falling edge General-Purpose Input/Output Cycles 33-MHz External Bus Min Max 10 10 5 5 5 5 10 10 10 10 5 5 5 5 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet 115 t1 t2 SA25-SA0 GPIO_CSx IOW IOR IOCHRDY SD7-SD0/SD15-SD0 (Write) D7-D0/D15-D0 (Read) t2 t1 Notes: See the ISA bus section on page 105 for detailed timings between these signals. Figure 50. I/O Decode (R/W), Address Decode Only SA25-SA0 t6 t4 GPIO_CSx t3 t5 IOW IOR IOCHRDY SD7-SD0/SD15-SD0 (Write) SD7-SD0/SD15-SD0 (Read) Notes: See the ISA bus section on page 105 for detailed timings between these signals. Figure 51. I/O Decode (R/W), Command Qualified 116 ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet t8 t8 t7 SA25-SA0 GPIO_CSx IOW IOR IOCHRDY 60h or 64h t7 60h or 64h SD7-SD0 (Write) SD7-SD0 (Read) Notes: See the ISA bus section on page 105 for detailed timings between these signals. Figure 52. I/O Decode (R/W), GPIO_CSx as 8042CS Timing t10 t9 SA25-SA0 GPIO_CSx MEMW MEMR IOCHRDY SD7-SD0 (Write) SD7-SD0 (Read) t9 t10 Notes: See the ISA bus section on page 105 for detailed timings between these signals. Figure 53. Memory CS Decode (R/W), Address Decode Only ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet 117 SA25-SA0 t14 GPIO_CSx t12 t11 t13 MEMW MEMR IOCHRDY SD7-SD0/SD15-SD0 (Write) SD7-SD0/SD15-SD0 (Read) Notes: See the ISA bus section on page 105 for detailed timings between these signals. Figure 54. Memory CS Decode (R/W), Command Qualified 118 ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet Table 42. Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13a t13b t14 t15 t16 t17a t17b t18a t18b PC Card Cycles--ElanSC400 Microcontroller Only Notes 1,2 1, 3 14 Parameter Description REG_x, SA setup to command active Command pulse width SA hold and write data valid from command inactive WAIT_AB Active from command active Command hold from WAIT_AB inactive SD setup before read command inactive SD valid from read command inactive SD valid from WAIT_AB inactive IOIS16 setup before command inactive MCEH_x delay from IOIS16 active IOIS16 delay from valid SA Setup, DACK assertion to DMA I/O command active Pulse width, DMA I/O write command Pulse width, DMA I/O read command Hold, DMA I/O command inactive to DACK inactive DMA I/O command setup to TC active TC pulse width SD setup to DMA IOW active SD valid delay from DMA IOR active SD hold from DMA IOW inactive SD hold from DMA IOR inactive 33-MHz External Bus Min ST-10 CT-10 RT-10 (C-2)*T-10 2T 2T+10 0 T+10 3T+10 T-10 35 145 220 700 60 15 62 -241 100 0 0 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns , 1, 3 1 1 1 1 1 Notes: 1. T is the nominal period of the selected clock: in Standard mode, this is the 125-ns ISA bus clock; in Enhanced mode, it is the 30-ns local bus clock. 2. S determines the setup time as programmed into the Setup Timing Register selected from one of four timing sets. Its value can be programmed to a range of 1 to 4096 * 63. 3. C determines the command active time as programmed into the Command Timing Register selected from one of four timing sets. Its value can be programmed to a range of 1 to 4096 * 63. 4. R determines the recovery time as programmed into the Recovery Timing Register selected from one of four timing sets. Its value can be programmed to a range of 1 to 4096 * 63. ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet 119 t3 SA25-SA0 REG_A REG_B MCEL_A MCEL_B MCEH_A MCEH_B t2 t1 t4 OE t8 WAIT_AB t5 t6 t7 SD15-SD8 SD7-SD0 DBUFOE DBUFRDL DBUFRDH Three-state or Not Valid for Attribute Memory Read Cycles Read Cycle Data Figure 55. PC Card Attribute Memory Read Cycle (ElanSC400 Microcontroller Only) Table 43. Mode Byte Access Word Access Odd-Byte-Only Access PC Card Attribute Memory Read Function (ElanSC400 Microcontroller Only) REG_x L L L L MCEH_x H H L L MCEL_x L L L H SA0 L H Indeterminate Indeterminate OE L L L L WE H H H H SD15-SD8 Three-state Three-state Not valid Not valid SD7-SD0 Even byte Not valid Even byte Three-state 120 ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet t3 SA25-SA0 REG_A REG_B MCEL_A MCEL_B MCEH_A MCEH_B t1 t4 WE WAIT_AB t2 t5 SD15-SD8 SD7-SD0 DBUFOE DBUFRDL DBUFRDH Not Valid for Attribute Memory Write Cycles Write Cycle Data Figure 56. PC Card Attribute Memory Write Cycle (ElanSC400 Microcontroller Only) Table 44. PC Card Attribute Memory Write Function (ElanSC400 Microcontroller Only) Mode Byte Access Word Access Odd-Byte-Only Access REG_x L L L L MCEH_x H H L L MCEL_x L L L H SA0 L H Indeterminate Indeterminate OE H H H H WE L L L L SD15-SD8 Indeterminate Indeterminate Indeterminate Indeterminate SD7-SD0 Even byte Indeterminate Even byte Indeterminate ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet 121 t3 SA25-SA0 REG_A REG_B MCEL_A MCEL_B MCEH_A MCEH_B t2 t1 t4 OE t8 WAIT_AB t5 t6 t7 SD15-SD0 DBUFOE DBUFRDL DBUFRDH Read Cycle Data Figure 57. PC Card Common Memory Read Cycle (ElanSC400 Microcontroller Only) Table 45. Mode Byte Access Word Access Odd-Byte-Only Access PC Card Common Memory Read Function (ElanSC400 Microcontroller Only) REG_x H H H H MCEH_x H H L L MCEL_x L L L H SA0 L H Indeterminate Indeterminate OE L L L L WE H H H H SD15-SD8 Three-state Three-state Odd byte Odd byte SD7-SD0 Even byte Odd byte Even byte Three-state 122 ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet t3 SA25-SA0 REG_A REG_B MCEL_A MCEL_B MCEH_A MCEH_B t1 t4 WE WAIT_AB t2 t5 SD15-SD0 DBUFOE DBUFRDL DBUFRDH Write Cycle Data Figure 58. PC Card Common Memory Write Cycle (ElanSC400 Microcontroller Only) Table 46. PC Card Common Memory Write Function (ElanSC400 Microcontroller Only) Mode Byte Access Word Access Odd-Byte-Only Access REG_x H H H H MCEH_x H H L L MCEL_x L L L H SA0 L H Indeterminate Indeterminate OE H H H H WE L L L L SD15-SD8 SD7-SD0 Indeterminate Even byte Indeterminate Odd byte Odd byte Odd byte Even byte Indeterminate ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet 123 t11 SA25-SA0 REG_A REG_B t9 t2 t5 t1 t4 IOR t8 t6 t7 t3 WAIT_AB MCEL_A MCEL_B MCEH_A MCEH_B WP_x (IOCS16_x) SD15-SD0 DBUFOE DBUFRDL DBUFRDH t10 Read Cycle Data Figure 59. PC Card I/O Read Cycle Table 47. PC Card I/O Read Function (ElanSC400 Microcontroller Only) Mode Byte Access Word Access High Byte Only REG_x L L L L MCEH_x H H L L MCEL_x L L L H SA0 L H Indeterminate Indeterminate IOR L L L L IOW H H H H SD15-SD8 Three-state Three-state Odd byte Odd byte SD7-SD0 Even byte Odd byte Even byte Three-state 124 ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet t11 SA25-SA0 REG_A REG_B t9 t1 IOW WAIT_AB MCEL_A MCEL_B MCEH_A MCEH_B WP_x (IOCS16_x) SD15-SD0 DBUFOE DBUFRDL DBUFRDH Write Cycle Data t10 t4 t2 t5 t3 Figure 60. PC Card I/O Write Cycle Table 48. PC Card I/O Write Function (ElanSC400 Microcontroller Only) Mode Byte Access Word Access Odd-Byte-Only Access REG_x MCEH_x MCEL_x L L L L H H L L L L L H SA0 L H Indeterminate Indeterminate IOR H H H H IOW L L L L SD15-SD8 Indeterminate Indeterminate Odd byte Odd byte SD7-SD0 Even byte Odd byte Even byte Indeterminate ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet 125 t14 REG_A, REG_B, (DACK) MCEL_A, MCEL_B, MCEH_A, MCEH_B OE, IOR t12 IOW t15 WE (TC) t16 t13a t17a SD15-SD0 DBUFOE DBUFRDL DUBFRDH DMA Data to Card t18a Figure 61. PC Card DMA Read Cycle (Memory Read to I/O Write) Table 49. Mode Byte Access Word Access DACK H H PC Card DMA Read Function (ElanSC400 Microcontroller Only) MCEH_x H L MCEL_x L L OE H H WE TC TC IOR H H IOW L L SD15-SD8 Odd byte SD7-SD0 Even byte DREQ L L Indeterminate Even byte 126 ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet REG_A, REG_B, (DACK) MCEL_A, MCEL_B, MCEH_A, MCEH_B WE, IOW t12 IOR t15 t16 OE (TC) t17b SD15-SD0 DBUFOE DBUFRDL DBUFRDH DMA Data from Card t13b t14 t18b Figure 62. PC Card DMA Write Cycle (I/O Read to Memory Write) Table 50. PC Card DMA Write Function (ElanSC400 Microcontroller Only) Mode Byte Access Word Access DACK H H DREQ L L MCEH_x H L MCEL_x L L OE TC TC WE H H IOR L L IOW H H SD15-SD8 Odd byte SD7-SD0 Even byte Indeterminate Even byte ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet 127 Table 51. Symbol t1a t1b t2 t3 t4 t5 t6 t7 t8 t9 t11a t11b t12a t12b t13 t14 t15 LCD Graphics Controller Cycles--ElanSC400 Microcontroller Only Notes 1 Parameter Description SCK period, monochrome panel SCK period, color STN panel SCK High time SCK Low time Setup, data to SCK falling edge Hold, LCD_data from SCK falling edge Width, LC Setup, FRM to LC falling Hold, FRM from LC falling Delay, LC falling to M phase change Delay, power-on sequencing, LVDD to signals Delay, power-on sequencing, signals to LVEE Delay, power-off sequencing, LVEE to signals, normal power-down Delay, power-off sequencing, signals to LVDD, normal power-down Delay, LVEE to LCD_SIGNALS off, emergency power-down Delay, LCD_SIGNALS off to LVDD off, emergency power-down Delay, emergency power-off sequencing from BL2 edge 33-MHz External Bus Min 4T 2T T T T-15 T-15 8T Max Unit ns ns ns ns ns ns ns ns ns 1 1 1 1 1 1,2 1,2 0 3 4 5 6 15 62.5 62.5 500 500 ns ms ms ms ms ns ns 7.8 7.8 62.5 62.5 0 0 0 10 s Notes: 1. T = period of internal video dot clock--programmable via the Pixel Clock Control Register. 2. Programmable to within resolution of 8T intervals (single-screen mode) or 16T intervals (dual-screen mode). 3. Programmable through PMU Control Register 1, bits 2-0. 4. Programmable through PMU Control Register 1, bits 5-3. 5. Programmable through PMU Control Register 2, bits 2-0. 6. Programmable through PMU Control Register 2, bits 5-3. t2 t4 SCK LCDD7- LCDD0 t1a,b t3 t5 t7 t6 LC t8 t9 FRM M Figure 63. Graphics Panel Interface Timing (ElanSC400 Microcontroller Only) 128 ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet t12b LVDD t11a t11a t15 t14 t11b Graphics Panel Interface Signals (Figure 63) LVEE BL2 Battery Failure Normal Operation t11b t12a t13 Figure 64. Graphics Panel Power Sequencing (ElanSC400 Microcontroller Only) ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet 129 THERMAL CHARACTERISTICS The thermal specifications for the ElanSC400 and ElanSC410 microcontrollers are given as a TCASE (the case temperature) specification. The 33-MHz and 66-MHz devices are specified for operation when TCASE is with the range of 0C-+95C. The 100-MHz device is specified for operation when TCASE is within the range of 0C-+85C. TCASE can be measured in any environment to determine whether the microcontroller is within specified operating range. The case temperature should be measured at the center of the top surface opposite the solder balls. The ambient temperature (TA) is guaranteed as long as TCASE is not violated. The ambient temperature can be calculated from J-T and JA from the following equations: TJ = TCASE + P * J-T TA = TJ - P * JA TCASE = TA + P * (JA - J-T) where: TJ is the junction temperature (C). TA is the ambient temperature (C). TCASE is the case temperature (C). J-T is the junction-to-case thermal resistance (C/W). JA is the junction-to-ambient thermal resistance (C/W). P is the maximum power consumption (W). The values for JA and J-T are given in Table 52 for the BGA 292 package. These numbers are valid only for packages with all 292 balls soldered to a board with two power planes and two signal planes. Table 53 shows the TA allowable (without exceeding TCASE) at various airflows and operating frequencies. P is calculated using the ICC at 3.3 V as tabulated in the DC Characteristics section beginning on page 86. Table 52. Thermal Resistance J-T and JA (C/W) for the 292-BGA Package) Airflow in Feet/Minute (m/s) Thermal Resistance JA J-T 0 (0) 25.0 6.2 200 (1.01) 20.5 6.2 400 (2.03) 19.0 6.2 600 (3.04) 18.1 6.2 800 (4.06) 17.4 6.2 Table 53. Maximum TA at Various Airflows in C Airflow in Feet/Minute (m/s) 0 200 (1.01) 86.4 77.5 59.0 400 (2.03) 87.3 79.3 61.7 600 (3.04) 87.8 80.4 63.4 800 (4.06) 88.3 81.3 64.6 Maximum TA at 33 MHz at 66 MHz at 100 MHz (0) 83.7 72.0 50.8 130 ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet PHYSICAL DIMENSIONS--BGA 292--PLASTIC BALL GRID ARRAY A1 CORNER A1 CORNER I.D. 27.00 BSC 21.20 22.80 17.00 MIN A 3X 0.50 R. ENCAPSULATION 27.00 BSC 4X .20 0.50 0.70 0.51 0.61 TOP SIDE (DIE SIDE) B 0.15 C 0.15 C C 2.11 2.61 A SIDE VIEW SEATING PLANE 0.15 C DETAIL A SCALE:NONE .30 S C A B .10 S C 24.13 BSC (DATUM A) A1 CORNER A1 CORNER I.D. A B C D E F G H J K L M N P R T U V W Y 0.60 0.90 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0.635 BSC (DATUM B) 4.445 3X 24.13 BSC ALIGNMENT MARK 0.75 SQ 3X THERMAL BALLS 0.635 BSC BOTTOM VIEW 1.27 BSC ALL ROWS AND COLUMNS 16-038-BGA292-2_AB ES114 9.14.98 lv ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet 131 Trademarks (c) 1998 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo and combinations thereof, Am186, Am188, E86, K86, Elan, Comm86, and Systems in Silicon are trademarks, and Am386 and Am486 are registered trademarks of Advanced Micro Devices, Inc. FusionE86 is a service mark of Advanced Micro Devices, Inc. Microsoft and Windows are registered trademarks of Microsoft Corp. Other product names used in this publication are for identification purposes and may be trademarks of their respective companies. 132 ElanTMSC400 and ElanSC410 Microcontrollers Data Sheet |
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